74ABT374CSJ Fairchild Semiconductor, 74ABT374CSJ Datasheet

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74ABT374CSJ

Manufacturer Part Number
74ABT374CSJ
Description
IC FLIP FLOP OCT D-TYPE 20SOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Type
D-Type Busr
Datasheet

Specifications of 74ABT374CSJ

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
200MHz
Delay Time - Propagation
3.2ns
Trigger Type
Positive Edge
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74ABT374CSC
74ABT374CSJ
74ABT374CMSA
74ABT374CMTC
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
3-STATE outputs for bus-oriented applications
Output sink capability of 64mA, source capability of
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down cycle
Nondestructive, hot-insertion capability
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number
MSA20
MTC20
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150,
5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
General Description
The ABT374 is an octal D-type flip-flop featuring sepa-
rate D-type inputs for each flip-flop and 3-STATE outputs
for bus-oriented applications. A buffered Clock (CP) and
Output Enable (OE) are common to all flip-flops.
Package Description
December 2007
www.fairchildsemi.com

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74ABT374CSJ Summary of contents

Page 1

... Nondestructive, hot-insertion capability Ordering Information Package Order Number Number 74ABT374CSC 74ABT374CSJ 74ABT374CMSA 74ABT374CMTC Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev ...

Page 2

... Operation of the OE input does not affect the state of the flip-flops. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Pin Descriptions Pin Names Description D – ...

Page 3

... Free Air Ambient Temperature A V Supply Voltage Minimum Input Edge Rate Data Input Enable Input Clock Input ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Parameter Parameter 3 Rating –65°C to +150°C –55°C to +125°C –55°C to +150°C –0.5V to +7.0V – ...

Page 4

... Outputs Enabled CCT I /Input CC Outputs 3-STATE Outputs 3-STATE I Dynamic I No Load CCD CC Notes: 2. For 8-bit toggling, I 0.8mA/MHz. CCD 3. Guaranteed, but not tested. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 V Conditions CC Recognized HIGH Signal Recognized LOW Signal Min. I –18mA IN Min. I –3mA OH I –32mA OH Min ...

Page 5

... SOIC and SSOP package. Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay PLH PHL t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Conditions 5.0 T 25° 5.0 T 25° 5.0 T 25°C A 5.0 T 25° ...

Page 6

... LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 10. The 3-STATE delay Time is dominated by the RC network (500 , 250pF) on the output and has been excluded from the datasheet. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 T +25°C T – ...

Page 7

... This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Capacitance Symbol Parameter C Input Capacitance IN (16) C Output Capacitance OUT Note: 16 measured at frequency f OUT ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 T –40°C to +85° 4.5V–5. (11) 8 Outputs Switching Max. 1.0 1.0 1 ...

Page 8

... Figure 1. Standard AC Test Load Amplitude Rep. Rate AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 5. Propagation Delay, Pulse Width Waveforms ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.5.0 Input Pulse Requirements t w 3.0V 1 MHz 500ns Figure 3 ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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