74LCX374BQX Fairchild Semiconductor, 74LCX374BQX Datasheet - Page 2

• Manufacturer Part Number: 74LCX374BQX
• Description: IC FLIP FLOP OCT D LV 20-DQFN
• Manufacturer: Fairchild Semiconductor
• Series: 74LCXr
• Type: D-Type Busr

Specifications of 74LCX374BQX

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 150MHz
• Delay Time - Propagation: 8.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-WQFN Exposed Pad, 20-DQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2006 Fairchild Semiconductor Corporation
74LCX374 Rev. 1.6.0
Connection Diagrams
Pin Description
D
CP
OE
O
0
0
–D
–O
7
7
Pin Names
Pad Assignments for DQFN
GND
SOIC, SOP, SSOP, TSSOP
OE
O
O
O
O
D
D
D
D
Pin Assignments for
0
0
1
1
2
2
3
3
O
O
O
O
D
D
D
D
0
0
1
1
2
2
3
3
1
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
(Top View)
GND
OE
10
1
Data Inputs
Clock Pulse Input
Output Enable Input
3-STATE Outputs
V
CP
11
20
CC
20
19
18
17
16
15
14
13
12
11
19
18
17
16
15
14
13
12
Description
O
D
D
O
O
D
D
O
V
O
D
D
O
O
D
D
O
CP
7
7
6
6
5
5
4
4
CC
7
7
6
6
5
5
4
4
2
Logic Symbol
Truth Table
H
L
X
Z
O
Functional Description
The LCX374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
Please note that this diagram is provided only for the
understanding of logic operations and should not be
used to estimate propagation delays.
0
LOW Voltage Level
High Impedance
Immaterial
HIGH Voltage Level
Previous O
D
LOW-to-HIGH Transition
H
X
X
L
n
0
Inputs
OE
CP
before HIGH-to-LOW of CP
CP
D
O
L
X
0
0
O
D
1
1
D
O
2
2
D
O
3
3
O
D
4
4
OE
H
D
O
L
L
L
5
5
D
O
6
6
O
D
7
7
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Outputs
O
O
H
L
Z
n
0