74VHC574MTC Fairchild Semiconductor, 74VHC574MTC Datasheet - Page 2
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74VHC574MTC
Manufacturer Part Number
74VHC574MTC
Description
IC F/F OCTAL D-TYPE 3ST 20-TSSOP
Manufacturer
Fairchild Semiconductor
Series
74VHCr
Type
D-Type Busr
Datasheet
1.74VHC574MTC.pdf
(8 pages)
Specifications of 74VHC574MTC
Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
180MHz
Delay Time - Propagation
5.6ns
Trigger Type
Positive Edge
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Number Of Circuits
8
Logic Family
74VHC
Logic Type
D-Type Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
16.7 ns
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74VHC574MTC
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Company:
Part Number:
74VHC574MTCX
Manufacturer:
FSC
Quantity:
524
Part Number:
74VHC574MTCX
Manufacturer:
NS/国半
Quantity:
20 000
www.fairchildsemi.com
Functional Description
The VHC574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Truth Table
H
L
X
Z
LOW Voltage Level
High Impedance
HIGH Voltage Level
Immaterial
LOW-to-HIGH Transition
D
H
X
L
n
Inputs
CP
X
OE
H
L
L
Outputs
O
H
L
Z
n