MT9LSDT1672AG-10E Micron, MT9LSDT1672AG-10E Datasheet - Page 8

• Manufacturer Part Number: MT9LSDT1672AG-10E
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron

Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in the Burst Definition
Table.
to ensure compatibility
16, 32 Meg x 72 SDRAM DIMMs
SD9_18C16_32X72AG_C.p65 – Rev. C; Pub. 11/01
with future devices.
M11, M10 = “0, 0”
*Should program
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
Reserved* WB
11
A11
Mode Register Definition
10
A10
M9
0
1
9
A9
Op Mode
8
A8
7
A7
Programmed Burst Length
M8
Diagram
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
A6
5
M7
A5
0
-
4
A4
M3
BT
M6-M0
Defined
0
1
3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M5
A2
M1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
A0
Full Page
Reserved
Reserved
Reserved
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
8
NOTE: 1. For full-page accesses: y = 1,024 .
Length
Burst
Page
Full
(y)
2
4
8
2. For a burst length of two, A1-A9 select the block-
3. For a burst length of four, A2-A9 select the block-
4. For a burst length of eight, A3-A9 select the block-
5. For a full-page burst, the full row is selected and
6. Whenever a boundary of the block is reached
7. For a burst length of one, A0-A9 select the unique
Micron Technology, Inc., reserves the right to change products or specifications without notice.
of-two burst; A0 selects the starting column
within the block.
of-four burst; A0-A1 select the starting column
within the block.
of-eight burst; A0-A2 select the starting column
within the block.
A0-A9 select the starting column.
within a given sequence above, the following
access wraps within the block.
column to be accessed, and mode register bit M3
is ignored.
Starting Column
A2 A1 A0
(location 0-y)
0
0
0
0
1
1
1
1
128MB/256MB (x72, ECC)
n = A0-A9
Address:
A1 A0
168-PIN SDRAM DIMMs
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn, Cn + 1, Cn + 2
Table
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Type = Sequential
Order of Accesses Within a Burst
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
©2001, Micron Technology, Inc.
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0