MT9LSDT1672AG-10E Micron, MT9LSDT1672AG-10E Datasheet - Page 17

• Manufacturer Part Number: MT9LSDT1672AG-10E
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron

SPD CLOCK AND DATA CONVENTIONS
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ures 1 and 2).
SPD START CONDITION
which is a HIGH-to-LOW transition of SDA when SCL is
HIGH. The SPD device continuously monitors the SDA
and SCL lines for the start condition and will not re-
spond to any command until this condition has been
met.
SPD STOP CONDITION
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
16, 32 Meg x 72 SDRAM DIMMs
SD9_18C16_32X72AG_C.p65 – Rev. C; Pub. 11/01
SDA
SCL
Data states on the SDA line can change only during
All commands are preceded by the start condition,
All communications are terminated by a stop condi-
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
DATA STABLE
Data Validity
Figure 1
DATA
CHANGE
Acknowledge Response From Receiver
DATA STABLE
Figure 3
17
SPD ACKNOWLEDGE
cate successful data transfers. The transmitting de-
vice, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
knowledge after recognition of a start condition and its
slave address. If both the device and a WRITE opera-
tion have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop con-
dition to return to standby power mode.
SDA
SCL
Acknowledge is a software convention used to indi-
The SPD device will always respond with an ac-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Definition of Start and Stop
START
BIT
128MB/256MB (x72, ECC)
168-PIN SDRAM DIMMs
8
Figure 2
Acknowledge
9
©2001, Micron Technology, Inc.
STOP
BIT