MT9LSDT1672AG-10E Micron, MT9LSDT1672AG-10E Datasheet - Page 5

• Manufacturer Part Number: MT9LSDT1672AG-10E
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron

PIN DESCRIPTIONS*
*Pin numbers listed in module pinout order and do not necessarily correlate to symbols.
16, 32 Meg x 72 SDRAM DIMMs
SD9_18C16_32X72AG_C.p65 – Rev. C; Pub. 11/01
33, 34, 35, 36, 37, 38, 117,
118, 119, 120, 121,123
112-113, 130-131
PIN NUMBERS
42, 79, 125, 163
30, 45, 114, 129
28-29, 46-47,
27, 111, 115
63, 128
39, 122
81
83
DQMB0-DQMB7
RAS#, CAS#,
CKE0, CKE1
SYMBOL
BA0, BA1
CK0-CK3
S0#-S3#
A0-A11
WE#
SCL
WP
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
5
Command Inputs: RAS#, CAS#, and WE# (along with
S0#-S3#) define the command being entered.
Clock: CK0-CK3 are driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of CK. CK also increments the internal burst
counter and controls the output registers.
Clock Enable: CKE0-CKE1 activate (HIGH) and deacti-
vate (LOW) the CK0-CK3 signals. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all device banks idle), ACTIVE
POWER-DOWN (row ACTIVE in any device bank) or
CLOCK SUSPEND operation (burst access in progress).
CKE0-CKE1 are synchronous except after the device
enters power-down and self refresh modes, where
CKE0-CKE1 become asynchronous until after exiting
the same mode. The input buffers, including CK0-CK3,
are disabled during power-down and self refresh
modes, providing low standby power.
Chip Select: S0#-S3# enable (registered LOW) and
disable (registered HIGH) the command decoder. All
commands are masked when S0#-S3# are registered
HIGH. S0#-S3# are considered part of the command
code.
Input/Output Mask: DQMB is an input mask signal for
write accesses and an output enable signal for read
accesses. Input data is masked when DQMB is sampled
HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when
DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which device
bank the ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE
auto precharge) to select one location out of the
memory array in the respective device bank. A10 is
sampled during a PRECHARGE command to determine
if all device banks are to be precharged (A10 HIGH) or
device bank selected by BA0, BA1 (LOW). The address
inputs also provide the op-code during a LOAD MODE
REGISTER command.
Write Protect: Serial presence-detect hardware write
protect.
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
command (column-address A0-A9, with A10 defining
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MB/256MB (x72, ECC)
168-PIN SDRAM DIMMs
DESCRIPTION
©2001, Micron Technology, Inc.