MT9LSDT1672AG-10E Micron, MT9LSDT1672AG-10E Datasheet - Page 7

• Manufacturer Part Number: MT9LSDT1672AG-10E
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron

SDRAM COMPONENT DESCRIPTION
DRAMs that operate at 3.3V and include a synchro-
nous interface (all signals are registered on the positive
edge of the clock signal, CLK). The four banks of the x8
configured devices used for these modules are config-
ured as 4,096 bit-rows by 1,024 bit-columns, by 8 in-
put/output bits.
MODULE FUNCTIONAL DESCRIPTION
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the device bank and row to be accessed; BA0
and BA1 select the device bank, A0–A11 select the de-
vice row. The address bits A0–A9 registered coincident
with the READ or WRITE command are used to select
the starting device column location for the burst ac-
cess.
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions and device operation.
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this
100µs period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
least one COMMAND INHIBIT or NOP command hav-
ing been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
16, 32 Meg x 72 SDRAM DIMMs
SD9_18C16_32X72AG_C.p65 – Rev. C; Pub. 11/01
In general, the 128Mb SDRAMs are quad-bank
Read and write accesses to the SDRAM are burst
Prior to normal operation, the SDRAM must be ini-
SDRAMs must be powered up and initialized in a
Once in the idle state, two AUTO REFRESH cycles
Once the 100µs delay has been satisfied with at
DD
and V
DD
Q (simulta-
7
Register Definition
MODE REGISTER
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as
shown in the Mode Register Definition Diagram. The
mode register is programmed via the LOAD MODE REG-
ISTER command and will retain the stored information
until it is programmed again or the device loses power.
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
oriented, with the burst length being programmable,
as shown in the Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given READ
or WRITE command. Burst lengths of 1, 2, 4, or 8 loca-
tions are available for both the sequential and the in-
terleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached, as shown in the Burst Defini-
tion Table. The block is uniquely selected by A1–A9
when the burst length is set to two; by A2–A9 when the
burst length is set to four; and by A3–A9 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. Full-page bursts wrap within the
page if the boundary is reached, as shown in the Burst
Definition Table.
The mode register is used to define the specific mode
Mode register bits M0–M2 specify the burst length,
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MB/256MB (x72, ECC)
168-PIN SDRAM DIMMs
©2001, Micron Technology, Inc.