MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 51

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

Preliminary Information
13.7
Address 0063h to 0082h
Thirty-two Backplane input delay registers (BIDR0 to BIDR31) allow users to program the input bit delay for the
Backplane input data streams BSTi0-31. The possible adjustment is 7 3/4 of the data rate, in steps of 1/4 of
the data rate. The data rate can be either 2Mb/s, 4Mb/s, 8Mb/s, 16Mb/s, or 32Mb/s.
The BIDR0 to BIDR31 registers are configured as follows:
13.7.1
These five bits define how long in the cycle the serial interface receiver takes to recognize and stores the bit 0
from the BSTi input pins: i.e., start assuming a new frame. Input bit delay adjustment can range up to 7
periods forward with resolution of
This can be described as BIDn(4:0) = (no. of bits delay) / 4 For example, if BID(4:0) is set to 10011 (19), the
input bit delay = 19 *
Table 26 illustrates the bit delay selection.
Mode, n = 0 to15 for 32Mb/s Mode)
(where n = 0 to 31 for Non-32Mb/s
BIDRn Bit
Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Backplane Input Delay Bits 4-0 (BID4 - BID0 )
15-5
4-0
0 (Default)
Data Rate
1
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
/
Table 25 - Backplane Input Bit Delay Register (BIDRn) Bits
4
1/4
1/2
3/4
Table 26 - Backplane Input Bit Delay Programming Table
1
2
3
= 4
3
/
4.
1
/
Reserved
4
BID4
BID(4:0)
Name
bit period.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BID3
Corresponding Delay Bits
Reset
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
Reserved
Backplane Input Bit Delay Register
The binary value of these bits refers to the input
bit delay value for the Backplane input stream
BID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
BID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Description
BID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MT90870
3
/
4
bit
51