MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 16

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT90870
3.0
3.1
Various registers are used to control the input sampling point (delay) and the output advancement for the Local
and Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different
frame boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay
of zero such that Ch0 is the first channel that appears after the frame boundary.
By programming the Backplane or Local input channel delay registers, BCDR0-31 and LCDR0-15, users can
assign the Ch0 position to be located at any one of the channel boundaries in a frame. See Figure 8.
For delays within channel boundaries, the input bit delay programming can be used. The use of Input Channel
Delay in combination with Input Bit Delay enables the Ch0 position to be placed anywhere within a frame to a
resolution of 1/4 of the bit period.
3.2
In addition to the Input Channel Delay programming, the Input Bit Delay programming feature provides users
with greater flexibility when designing switch matrices for high speed operation. The input bit delay may be
programmed on a per-stream basis to accommodate delays created on PCM highways. For all streams the
delay is up to 7 3/4 bits with a resolution of 1/4 bit, for the selected data-rate.
See Figure 9 and Figure 10 for Input Bit Delay Timing at 16Mb/s and 8Mb/s data rates, respectively.
The Local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR15, corresponding to the
Local data streams, LSTi0 to LSTi15, and the Backplane input delay is defined by the Backplane Input Delay
registers, BIDR0 to BIDR31, which correspond to the Backplane data streams, BSTi0 to BSTi31.
16
BSTi0-31/LSTi0-15
BSTi0-31/LSTi0-15
Channel Delay = 2
Channel Delay = 0
Channel Delay = 1
BSTi0-31LSTi0-15
Input and Output Offset Programming
Input Channel Delay Programming (Backplane and Local Input Streams)
Input Bit Delay Programming (Backplane and Local Input Streams)
(Default)
FP8o
Figure 8 - Backplane and Local Input Channel Delay Timing Diagram (8Mb/s)
C8o
3
3
3
2
2
2
1 0
1 0
1 0
7
7
7
6
Channel Delay,1
6
6
Ch 0
5
5
Ch127
5
Ch127
4
4
4
3
3
3
2
2
2
Channel Delay, 2
1 0
1 0
1 0
7
7
7
6
6
6
5
5
5
Ch 1
Ch 0
Ch127
4
4
4
3
3
3
2
2
2
1 0
1 0
1 0
7
6
5
Ch0
4
3
6
6
2
5
Ch126
Ch125
5
1 0
4
4
3
3
2
2
Preliminary Information
1 0
1 0
7
7
7
6
6
6
5
5
Ch125
5
Ch127
Ch126
4
4
4
3
3
3
2
2
2
1 0
1 0
1 0
7 6
7 6
7 6