MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 15

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

Preliminary Information
2.3
The Backplane frame pulse (FP8i) is an 8kHz input signal active for 122ns or 244ns at the frame boundary. The
FPW bit in the Control Register
Table 16, Control Register Bits, for details.
The active state and timing of FP8i may conform either to the ST-BUS or to the GCI-BUS as shown in Figure 5,
Local Port Timing Diagram for 2,4,8 and 16Mb/s stream rates, and Figure 6, Backplane Port Timing Diagram
for 2, 4, 8, 16 and 32Mb/s stream rates. The MT90870 will automatically detect whether an ST-BUS or a GCI-
BUS style frame pulse is being used for the master frame pulse (FP8i). The active edge of the input clock (C8i)
shall be selected by the state of the Control Register bit C8IPOL. For the purposes of describing the device
operation, the remaining part of this document assumes the ST-BUS style frame pulse with a single width
frame pulse of 122ns and a falling active clock-edge, unless explicitly stated otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which
connect to the Local port. The Local frame pulses (FP8o, FP16o) will be provided in the same style as the
master frame pulse (FP8i). The polarity of C8o and C16o, at the Frame Boundary, can be controlled by the
Control Register bit, COPOL.
An analogue phase lock loop (APLL) is used to multiply the external clock frequency to generate an internal
clock signal operated at 131.072MHz. The MT90870 requires the cycle to cycle variation of the master clock
(C8i) to be less than 1ns to assure proper device operation.
2.4
The MT90870 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o
and FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being
switched. Figure 7, Backplane and Local Frame Pulse Alignment for Data Rates of 2Mb/s, 4Mb/s, 8Mb/s and
16Mb/s, refers.
For further details of Frame Pulse conditions and options see Section 13.1, Control Register (CR), Figure 17,
Frame Boundary Conditions, ST- BUS Operation, and Figure 18, Frame Boundary Conditions, GCI - BUS
Operation.
Figure 7 - Backplane and Local Frame Pulse Alignment for Data Rates of 2Mb/s, 4Mb/s, 8Mb/s
BSTi/BSTo0-31
BSTi/BSTo0-31
BSTi/BSTo0-31
BSTi/BSTo0-31
LSTi/LSTo0-15
LSTi/LSTo0-15
LSTi/LSTo0-15
LSTi/LSTo0-15
Backplane Frame Pulse Input and Master Input Clock Timing
Backplane Frame Pulse Input and Local Frame Pulse Output Alignment
(16Mb/s)
(16Mb/s)
(2Mb/s)
(4Mb/s)
(8Mb/s)
(2Mb/s)
(4Mb/s)
(8Mb/s)
FP8o
FP8i
C8o
C8i
CH
CH
CH0
CH0
0
0
CH
CH
1
1
CH0
CH0
CH
CH
CH1
CH1
2
2
must be set according to the applied pulse width. See Pin Description and
CH
CH
3
3
CH0
CH0
CH
CH
CH2
CH2
4
4
CH
CH
5
5
CH1
CH1
CH
CH
CH3
CH3
6
6
CH
CH
7
7
and 16Mb/s
CH
CH
CH4
CH4
8
8
CH
CH
9
9
CH2
CH2
CH
CH
10
CH5
10
CH5
CH
CH
11
11
CH1
CH1
CH
CH
12
12
CH6
CH6
CH
13
CH
13
CH3
CH3
CH
CH
14
CH7
14
CH7
CH
CH
15
15
CH
CH
16
16
CH8
CH8
CH
17
CH
CH4
CH4
17
CH
CH
18
18
CH9
CH9
CH
19
CH
19
CH2
CH2
CH
CH
20
20
CH10
CH10
CH
21
CH
CH5
CH5
21
MT90870
CH
CH
22
22
CH11
CH11
CH
CH
23
23
15