MT28F320J3 Micron, MT28F320J3 Datasheet - Page 25

• Manufacturer Part Number: MT28F320J3
• Description: Q-FLASHTM MEMORY
• Manufacturer: Micron

NOTE: 1. An invalid configuration code will result in both SR4 and SR5 being set.
SET BLOCK LOCK BITS COMMAND
enabled via a combination of block lock bits. The block
lock bits gate PROGRAM and ERASE operations. Using
the SET BLOCK LOCK BITS command, individual block
lock bits can be set. This command is invalid when the
ISM is running or when the device is suspended. SET
BLOCK LOCK BITS commands are executed by a two-
cycle sequence. The set block lock bits setup, along
with appropriate block address, is followed by the set
block lock bits confirm and an address within the block
to be locked. The ISM then controls the set lock bit
algorithm. When the sequence is written, the device
automatically outputs status register data when read
(see Figure 9). The CPU can detect the completion of
the set block lock bit event by analyzing the STS pin
output or status register bit SR7. Upon completion of
set block lock bits operation, status register bit SR4
should be checked for error. If an error is detected, the
status register should be cleared. The CEL remains in
read status register mode until a new command is is-
sued. This two-step sequence of setup followed by ex-
ecution ensures that lock bits are not accidentally set.
An invalid SET BLOCK LOCK BITS command results in
status register bits SR4 and SR5 being set to “1.” Also,
reliable operation occurs only when V
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
DQ1–DQ0 = STS Configuration Codes
00 = Default, RY/BY# level mode
01 = Pulse on Erase Complete
10 = Pulse on Program Complete
11 = Pulse on Erase or Program
A flexible block locking and unlocking scheme is
DQ7
(device ready) indication
Complete
2. When the device is configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of 250ns.
DQ6
DQ5
Configuration Coding Definitions
RESERVED
CC
and V
Used to control HOLD to a memory controller to prevent accessing
a Flash memory subsystem while any Flash device’s ISM is busy.
Used to generate a system interrupt pulse when any Flash device in
an array has completed a BLOCK ERASE or sequence of queued
BLOCK ERASEs; helpful for reformatting blocks after file system free
space reclamation or “cleanup.”
Used to generate a system interrupt pulse when any Flash device in
an array has completed a PROGRAM operation. Provides highest
performance for enabling continuous BUFFER WRITE operations.
Used to generate system interrupts to trigger enabling of Flash
arrays when either ERASE or PROGRAM operations are completed
and a common interrupt service routine is desired.
PEN
DQ4
are
Table 18
25
valid. When V
against any data change.
CLEAR BLOCK LOCK BITS COMMAND
all set block lock bits in parallel. This command is in-
valid when the ISM is running or the device is sus-
pended. The CLEAR BLOCK LOCK BITS command is
executed by a two-cycle sequence. First, a clear block
lock bits setup is written, followed by a CLEAR BLOCK
LOCK BITS CONFIRM command. Then the device au-
tomatically outputs status register data when read (see
Figure 9). The CPU can detect completion of the clear
block lock bits event by analyzing the STS pin output or
the status register bit SR7. When the operation is com-
pleted, status register bit SR5 should be checked. If a
clear block lock bits error is detected, the status register
should be cleared. The CEL remains in read status reg-
ister mode until another command is issued.
lock bits are not accidentally cleared. An invalid clear
block lock bits command sequence results in status
register bits SR4 and SR5 being set to “1.” Also, a reli-
able CLEAR BLOCK LOCK BITS operation can only oc-
cur when V
DQ3
The CLEAR BLOCK LOCK BITS command can clear
This two-step setup sequence ensures that block
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CC
PEN
NOTES
and V
DQ2
≤ V
128Mb, 64Mb, 32Mb
1
PENLK
PEN
Q-FLASH MEMORY
, lock bit contents are protected
are valid. If a CLEAR BLOCK
COMPLETE
PROGRAM
PULSE ON
DQ1
2
©2002, Micron Technology, Inc.
COMPLETE
PULSE ON
ERASE
DQ0
2