MT28F320J3 Micron, MT28F320J3 Datasheet - Page 20

• Manufacturer Part Number: MT28F320J3
• Description: Q-FLASHTM MEMORY
• Manufacturer: Micron

READ IDENTIFIER CODES COMMAND
initiates the IDENTIFIER CODE operation. Following
the writing of the command, READ cycles from ad-
dresses shown in Figure 2 retrieve the manufacturer,
device, and block lock configuration codes (see Table
15 for identifier code values). Page mode READs are
not supported in this read mode. To terminate the op-
eration, write another valid command. The READ
IDENTIFIER CODES command functions indepen-
dently of the V
when the ISM is off or the device is suspended. See
Table 15 for read identifier codes.
READ STATUS REGISTER COMMAND
ing the READ STATUS REGISTER command to deter-
mine the successful completion of programming, block
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
Writing the READ IDENTIFIER CODES command
The status register may be read at any time by writ-
PEN
voltage. This command is valid only
NOTE: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier
Manufacturer Compatibility Code
Device Code
• 32Mb
• 64Mb
• 128Mb
Block Lock Configuration
• Block is Unlocked
• Block is Locked
• Reserved for Future Use
2. X selects the specific block’s lock configuration code. See Figure 2 for the
codes. The lowest-order address line is A1. Data is always presented on the
low byte in x16 mode (upper byte contains 00h).
device identifier code memory map.
CODE
Identifier Codes
Table 15
20
erasure, or lock bit configuration. After writing this com-
mand, all subsequent READ operations output data
from the status register until another valid command is
written. Page mode READs are not supported in this
read mode. The status register contents are latched on
the falling edge of OE# or the first edge of CEx that
enables the device (see Table 2). To update the status
register latch, OE# must toggle to V
be disabled before further READs. The READ STATUS
REGISTER command functions independently of the
V
lock bits, or clear block lock bits command sequence,
only SR7 is valid until the ISM completes or suspends
the operation. Device I/O pins DQ0–DQ6 and DQ8–
DQ15 are placed in High-Z. When the operation com-
pletes or suspends (check status register bit 7), all con-
tents of the status register are valid during a READ.
ADDRESS
PEN
X0002h
00000h
00001h
00001h
00001h
voltage. During a program, block erase, set block
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
1
128Mb, 64Mb, 32Mb
DQ1–DQ7
DQ0 = 0
DQ0 = 1
(00) 89
(00) 16
(00) 17
(00) 18
DATA
Q-FLASH MEMORY
IH
or the device must
©2002, Micron Technology, Inc.