MT28F320J3 Micron, MT28F320J3 Datasheet - Page 23

• Manufacturer Part Number: MT28F320J3
• Description: Q-FLASHTM MEMORY
• Manufacturer: Micron

enables the suspended programming operation to con-
tinue. To resume the suspended erase, the user must
wait for the programming operation to complete be-
fore issuing the BLOCK ERASE RESUME command.
While block erase is suspended, the only other valid
commands are READ QUERY, READ STATUS REGIS-
TER, CLEAR STATUS REGISTER, CONFIGURE, and
BLOCK ERASE RESUME. After a BLOCK ERASE RESUME
command to the Flash memory is completed, the ISM
continues the block erase process. Status register bits
SR6 and SR7 automatically clear and STS (in default
mode) returns to V
mand is completed, the device automatically outputs
status register data when read. V
V
block erase suspension. Block erase cannot resume
during block erase suspend until PROGRAM opera-
tions are complete.
WRITE-TO-BUFFER COMMAND
to program the Flash device via the write buffer. A buffer
can be loaded with a variable number of bytes, up to
the buffer size, before writing to the Flash device. First,
the WRITE-to-BUFFER SETUP command is issued,
along with the block address (see Figure 4). Then, the
extended status register (XSR; see Table 17) informa-
tion is loaded and XSR7 indicates “buffer available”
status. If XSR7 = 0, the write buffer is not available. To
retry, issue the WRITE-to-BUFFER SETUP command
with the block address and continue monitoring XSR7
until XSR7 = 1. When XSR7 transitions to “1,” the buffer
is ready for loading new data. Then the part is given a
word/byte count with the block address. On the next
write, a device start address is given, along with the
write buffer data. Depending on the count, subsequent
writes provide additional device addresses and data.
All subsequent addresses must lie within the start ad-
dress plus the count.
parallel. Due to this parallel programming, maximum
programming performance and lower power are ob-
tained by aligning the start address at the beginning of
a write buffer boundary (i.e., A0–A4 of the start address
= 0).
FIRM command is issued, thus programming the ISM
to begin copying the buffer data to the Flash array. If
the device receives a command other than WRITE CON-
FIRM, an invalid command/sequence error is gener-
ated and status register bits SR5 and SR4 are set to “1.”
For additional BUFFER WRITEs, issue another WRITE-
to-BUFFER SETUP command and check XSR7.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
PENH
The write-to-buffer command sequence is initiated
The device internally programs many Flash cells in
When the final buffer data is given, a WRITE CON-
(the same V
PEN
OL
. After the ERASE RESUME com-
level used for block erase) during
PEN
must remain at
23
writing, and status register bit SR4 is set to a “1” to
indicate a program failure. The ISM only detects errors
for “1s” that do not successfully program to “0s.” When
a program error is detected, the status register should
be cleared. Note that the device does not accept any
more WRITE-to-BUFFER commands any time SR4 and/
or SR5 is set. In addition, if the user attempts to pro-
gram past an erase block boundary with a WRITE-to-
BUFFER command, the device aborts the WRITE-to-
BUFFER operation and generates an invalid command/
sequence error, and status register bits SR5 and SR4
are set to “1.”
V
V
“1.” Buffered write attempts with invalid V
voltages produce spurious results and should not be
attempted. Finally, the corresponding block lock bit
should be reset for successful programming. When a
BUFFERED WRITE is attempted while the correspond-
ing block lock bit is set, SR1 and SR4 are set to “1.”
BYTE/WORD PROGRAM COMMANDS
word program setup. This program setup (standard
40h or alternate 10h) is written, followed by a second
write that specifies the address and data (latched on
the rising edge of WE#). Next, the ISM takes over to
internally control the programming and program verify
algorithms. When the program sequence is written,
the device automatically outputs status register data
when read (see Figure 5). The CPU can detect the
completion of the program event by analyzing the STS
pin or status register bit SR7.
should be checked. The status register should be
cleared if a program error is detected. The ISM only
detects errors for “1s” that do not successfully program
to “0s.” The CEL remains in read status register mode
until it receives another command.
V
are set to “1” if a byte/word program is attempted while
V
be cleared for successful byte/word programs. If BYTE/
WORD is attempted while the corresponding block lock
bit is set, SR1 and SR4 are set to “1.”
PROGRAM SUSPEND COMMAND
gram interruption to read data in other Flash memory
locations. After starting the programming process, writ-
PEN
PEN
CC
PEN
If an error occurs during a WRITE, the device stops
Reliable BUFFERED WRITEs can only occur when
A two-cycle command sequence executes a byte/
Upon program completion, status register bit SR4
Reliable byte/word programs can only occur when
The PROGRAM SUSPEND command enables pro-
and V
= V
≤ V
≤ V
PENH
PENLK
PENLK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PEN
. If a BUFFERED WRITE is attempted while
, status register bits SR4 and SR3 are set to
. The corresponding block lock bit should
are valid. Status register bits SR4 and SR3
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
©2002, Micron Technology, Inc.
CC
and V
PEN