MT18VDDT6472PHG-265 Micron, MT18VDDT6472PHG-265 Datasheet - Page 7

• Manufacturer Part Number: MT18VDDT6472PHG-265
• Description: 512MB DDR SDRAM SODIMM
• Manufacturer: Micron

General Description
MT9VDDT6472PH, and MT9VDDT12872PH, are high-
speed CMOS, dynamic random-access, 128MB,
256MB, 512MB, and 1GB memory modules organized
in x72 (ECC) configuration. DDR SDRAM modules use
internally configured quad-bank DDR SDRAM devices.
tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effec-
tively consists of a single 2n-bit wide, one-clock-cycle
data transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM device during READs and by the
memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with
data for WRITEs.
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK. A phase-lock loop (PLL) device on
the module is used to redrive the differential clock sig-
nals to the DDR SDRAM devices to minimize system
clock loading.
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in
a programmed sequence. Accesses begin with the reg-
istration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the device bank and row to be accessed
(BA0, BA1 select device bank; A0–A11 select device row
for 128MB; A0–A12 select device row for 256MB and
512MB; and A0–A13 select device row for 1GB). The
address bits registered coincident with the READ or
WRITE command are used to select the device bank
and the starting device column location for the burst
access.
read or write burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
The Micron MT9VDDT1672PH, MT9VDDT3272PH,
DDR SDRAM modules use a double data rate archi-
A bidirectional data strobe (DQS) is transmitted
DDR SDRAM modules operate from differential
Read and write accesses to DDR SDRAM modules
DDR SDRAM modules provide for programmable
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
7
self-timed row precharge that is initiated at the end of
the burst access.
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible.
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM data
sheets.
PLL Operation
redrive the differential clock signals CK and CK# to the
DDR SDRAM devices to minimize system clock load-
ing.
Serial Presence-Detect Operation
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
mode of operation of DDR SDRAM device. This defini-
tion includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown
in the Mode Register Diagram. The mode register is
programmed via the MODE REGISTER SET command
(with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device
loses power (except for bit A8, which is self-clearing).
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
The pipelined, multibank architecture of DDR
An auto refresh mode is provided, along with a
A phase-lock loop (PLL) on the module is used to
DDR SDRAM modules incorporate serial presence-
The mode register is used to define the specific
Reprogramming the mode register will not alter the
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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C bus