MT18VDDT6472PHG-265 Micron, MT18VDDT6472PHG-265 Datasheet - Page 27

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MT18VDDT6472PHG-265

Manufacturer Part Number
MT18VDDT6472PHG-265
Description
512MB DDR SDRAM SODIMM
Manufacturer
Micron
Datasheet
Table 19: EEPROM Device Select Code
Most significant bit (b7) is sent first
Table 20: EEPROM Operating Modes
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
SELECT CODE
MODE
SDA OUT
Memory Area Select Code (two arrays)
Protection Register Select Code
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
SDA IN
SCL
t SU:STA
RW BIT
Figure 15: SPD EEPROM Timing Diagram
1
0
1
1
0
0
t F
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
t HD:STA
t LOW
t AA
V
V
V
V
IH
IH
IH
IH
WC
V
V
or V
or V
or V
or V
IL
IL
IL
IL
IL
IL
t HIGH
t HD:DAT
b7
BYTES
DEVICE TYPE IDENTIFIER
1
0
27
1
1
1
1
16
1
t DH
b6
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
0
1
200-PIN DDR SDRAM SODIMM
INITIAL SEQUENCE
t R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t SU:DAT
b5
1
1
b4
0
0
SA2
SA2
b3
CHIP ENABLE
©2004 Micron Technology, Inc. All rights reserved.
SA1
SA1
b2
t SU:STO
t BUF
ADVANCE
SA0
SA0
b1
UNDEFINED
RW
RW
RW
b0

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