MT18VDDT6472PHG-265 Micron, MT18VDDT6472PHG-265 Datasheet - Page 4

• Manufacturer Part Number: MT18VDDT6472PHG-265
• Description: 512MB DDR SDRAM SODIMM
• Manufacturer: Micron

Table 5:
Refer to Pin Assignment Tables on page 3 for pin number and symbol correlation.
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
71, 72, 73, 74, 79, 80, 83,
105, 106, 107, 108, 109,
99 (A12), 100, 101,102,
11, 25, 47, 61, 77, 133,
12, 26, 48, 62, 78, 134,
110, 111, 112, 115,
PIN NUMBERS
118, 119, 120
148, 170, 184
147,169, 183
123
117, 116
35, 37
121
96
84
(A13)
Pin Descriptions
WE#, CAS#, RAS#
(256MB, 512MB)
DQS0–DQS8
DM0–DM8
CK0, CK0#
SYMBOL
BA0, BA1
CB0–CB7
(128MB)
A0–A11
A0–A12
A0–A13
CKE0,
(1GB)
S0#
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
Output
Output
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK and CK# are differential clock inputs distributed
through an on-board PLL to all devices. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK#. Output data (DQ and DQS) is
referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers.and output drivers. Taking CKE LOW
provides PRECHARGE POWER- DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any device bank). CKE is synchronous for POWER-
DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
Chip Select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All com- mands are masked when
S# is registered HIGH. S# is considered part of the command
code.
Bank Address: BA0, BA1 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: A0-A11/A12 provide the row address for ACTIVE
commands, and the column address, and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Check Bits.
4
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2004 Micron Technology, Inc. All rights reserved.
DD
is applied.
ADVANCE