LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 142

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Timers
9.1
9.2
9.2.1
9.2.2
142
Block Diagram
Figure 9-1. GPTM Module Block Diagram
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two
16-bit load/initialization registers and their associated control functions. The exact functionality of
each GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see
page 153), the GPTM TimerA Mode (GPTMTAMR) register (see page 154), and the GPTM
TimerB Mode (GPTMTBMR) register (see page 155). When in one of the 32-bit modes, the timer
can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its
two 16-bit timers configured in any combination of the 16-bit modes.
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all
control registers are cleared and in their default states. Counters TimerA and TimerB are initialized
to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 163) and the GPTM TimerB Interval Load (GPTMTBILR)
register (see page 164). The prescale counters are initialized to 0x00: the GPTM TimerA
Prescale (GPTMTAPR) register (see page 167) and the GPTM TimerB Prescale (GPTMTBPR)
register (see page 168).
32-Bit Timer Operating Modes
Note:
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and
their configuration.
Interrupt
TimerA
Interrupt
TimerB
System
Clock
The odd-numbered CCP pins are used for 16-bit input and the even-numbered CCP pins
are used for 32-bit input.
Interrupt / Config
GPTMCFG
GPTMCTL
GPTMIMR
GPTMMIS
GPTMICR
GPTMRIS
GPTMTAMATCHR
GPTMTBMATCHR
TimerA Control
TimerB Control
GPTMTAPMR
GPTMTBPMR
GPTMTAILR
GPTMTAMR
GPTMTBILR
GPTMTBMR
GPTMTAPR
GPTMTBPR
Preliminary
TA Comparator
TB Comparator
GPTMTBR
0x0000 (Down Counter Modes )
0x0000 (Down Counter Modes )
GPTMAR
En
En
Clock / Edge
Clock / Edge
RTC Divider
Detect
Detect
CCP (even)
CCP (odd)
July 5, 2006