LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 260

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
General-Purpose Input/Outputs (GPIOs)
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x420
Type R/W, reset -
260
Bit/Field
31:8
RO
RO
31
15
0
0
RO
RO
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 260), GPIO Pull-Up Select (GPIOPUR) register (see page 266), and GPIO Digital
Enable (GPIODEN) register (see page 269) are not committed to storage unless the GPIO Lock
(GPIOLOCK) register (see page 271) has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register (see page 272) have been set to 1.
Important:
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
®
All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The
JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1
and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins
back to their default state.
RO
RO
28
12
microcontroller. If the program code loaded into flash immediately changes the JTAG
0
0
reserved
RO
RO
27
11
0
0
Type
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
RO
23
0
7
-
R/W
RO
22
0
6
-
R/W
RO
21
0
5
-
R/W
RO
20
0
4
-
AFSEL
R/W
RO
19
0
3
-
R/W
RO
18
0
2
-
R/W
RO
17
0
1
June 02, 2008
-
R/W
RO
16
0
0
-