LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 10

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-9.
Figure 15-10. MICROWIRE Frame Format (Single Frame) .................................................................... 428
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 429
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 429
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10. Master Burst RECEIVE .................................................................................................. 467
Figure 16-11. Master Burst RECEIVE after Burst SEND ........................................................................ 468
Figure 16-12. Master Burst SEND after Burst RECEIVE ........................................................................ 469
Figure 16-13. Slave Command Sequence ............................................................................................ 470
Figure 17-1.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 19-1.
Figure 22-1.
Figure 22-2.
Figure 22-3.
Figure 22-4.
Figure 22-5.
Figure 22-6.
Figure 22-7.
Figure 22-8.
Figure 22-9.
Figure 22-10. Power-On Reset Timing ................................................................................................. 621
Figure 22-11. Brown-Out Reset Timing ................................................................................................ 621
Figure 22-12. Software Reset Timing ................................................................................................... 621
Figure 22-13. Watchdog Reset Timing ................................................................................................. 621
Figure 23-1.
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Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 427
I
I
START and STOP Conditions ......................................................................................... 460
Complete Data Transfer with a 7-Bit Address ................................................................... 461
R/S Bit in First Byte ........................................................................................................ 461
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 464
Master Single RECEIVE ................................................................................................. 465
Master Burst SEND ....................................................................................................... 466
USB Module Block Diagram ........................................................................................... 494
Analog Comparator Module Block Diagram ..................................................................... 582
Structure of Comparator Unit .......................................................................................... 583
Comparator Internal Reference Structure ........................................................................ 584
100-Pin LQFP Package Pin Diagram .............................................................................. 594
Load Conditions ............................................................................................................ 613
I
Hibernation Module Timing ............................................................................................. 617
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 617
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 618
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 618
JTAG Test Clock Input Timing ......................................................................................... 619
JTAG Test Access Port (TAP) Timing .............................................................................. 619
External Reset Timing (RST) .......................................................................................... 620
100-Pin LQFP Package .................................................................................................. 622
2
2
2
C Block Diagram ......................................................................................................... 459
C Bus Configuration .................................................................................................... 460
C Timing ..................................................................................................................... 616
Preliminary
2
C Bus ............................................................... 461
June 02, 2008