LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 642
LM3S5652
Manufacturer Part Number
LM3S5652
Description
Lm3s5652 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5652.pdf
(703 pages)
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Company:
Part Number:
LM3S5652-IQR50-A0
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Texas Instruments
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10 000
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Part Number:
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Manufacturer:
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Signal Tables
642
Analog
Comparators
Controller Area
Network
General-Purpose
Timers
I2C
JTAG/SWD/SWO
Power
Function
ADC3
ADC4
ADC5
C0+
C0-
CAN0Rx
CAN0Tx
CCP0
CCP1
CCP2
CCP3
CCP4
CCP5
I2C0SCL
I2C0SDA
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDA
HIB
LDO
VBAT
Pin Name
Number
Pin
64
63
56
58
61
62
57
25
26
16
47
27
52
51
49
52
50
49
51
10
13
24
29
36
39
44
53
60
33
37
11
6
8
4
7
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
-
-
-
-
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Buffer
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
OD
OD
OD
ADC 3 input
ADC 4 input
ADC 5 input
Analog comparator 0 positive input
Analog comparator 0 negative input
CAN module 0 receive
CAN module 0 transmit
Capture/Compare/PWM 0
Capture/Compare/PWM 1
Capture/Compare/PWM 2
Capture/Compare/PWM 3
Capture/Compare/PWM 4
Capture/Compare/PWM 5
I2C module 0 clock
I2C module 0 data
JTAG/SWD CLK
JTAG TMS and SWDIO
JTAG TDO and SWO
JTAG/SWD CLK
JTAG TDI
JTAG TDO and SWO
JTAG TMS and SWDIO
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
An output that indicates the processor is in
hibernate mode.
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
Description
June 02, 2008
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