LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 540

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
18.2.2.1 Endpoints
18.2.2.2 IN Transactions as a Host
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The endpoint registers are used to control the USB endpoint interfaces used to communicate with
device(s) that are connected. There is a dedicated bidirectional control IN/OUT interface, three
configurable OUT interfaces, and three configurable IN interfaces.
The dedicated control interface can only be used for control transactions to endpoint 0 of devices.
These control transactions are used during enumeration or other control functions that communicate
using endpoint 0 of devices. This control endpoint shares the first 64 bytes of the USB controller’s
FIFO RAM for IN and OUT transactions. The remaining IN and OUT interfaces can be configured
to communicate with control, bulk, interrupt, or isochronous device endpoints.
These USB interfaces can be used to simultaneously schedule as many as three independent OUT
and three independent IN transactions to any endpoints on any device. The IN and OUT controls
are paired in three sets of registers. However, they can be configured to communicate with different
types of endpoints and different endpoints on devices. For example, the first pair of endpoint controls
can be split so that the OUT portion is communicating with a device’s bulk OUT endpoint 1, while
the IN portion is communicating with a device’s interrupt IN endpoint 2.
Before accessing any device, whether for point-to-point communications or for communications via
a hub, the relevant USBRXFUNCADDRn or USBTXFUNCADDRn registers need to be set for each
receive or transmit endpoint to record the address of the device being accessed.
The USB controller also supports connections to devices through a USB hub by providing a register
that specifies the hub address and port of each USB transfer. The FIFO address and size are
customizable and can be specified for each USB IN and OUT transfer. This includes allowing one
FIFO per transaction, sharing a FIFO across transactions, and allowing for double-buffered FIFOs.
IN transactions are handled in a similar manner to the way in which OUT transactions are handled
when the USB controller is in Device mode except that the transaction first needs to be initiated by
setting the REQPKT bit in USBCSRL0. This indicates to the transaction scheduler that there is an
active transaction on this endpoint. The transaction scheduler then sends an IN token to the target
device. When the packet is received and placed in the receive FIFO, the RXRDY bit in USBCSRL0
is set and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now
be unloaded from the FIFO.
When the packet has been unloaded, RXRDY should be cleared. The AUTOCL bit in the
USBRXCSRHn register can be used to have RXRDY automatically cleared when a maximum-sized
packet has been unloaded from the FIFO. There is also an AUTORQ bit in USBRXCSRHn which
causes the REQPKT bit to be automatically set when the RXRDY bit is cleared. The AUTOCL and
AUTORQ bits can be used with DMA accesses to perform complete bulk transfers without main
processor intervention. When the RXRDY bit is cleared, the controller will send an acknowledge to
multiple of 64-byte packets (64, 128, 192, or 256 bytes). This allows for efficient use of double
buffering or packet splitting (described further in the following sections).
Interrupt.
twice the maximum packet size if double buffering is used.
Isochronous.
Control.
However, in most cases the USB controller should use the dedicated control endpoint to
communicate with a device’s endpoint 0.
It is also possible to specify a separate control endpoint to communicate with a device.
Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or
Isochronous endpoints are more flexible and can be up to 1023 bytes.
Preliminary
June 02, 2008