LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 213
LM3S5652
Manufacturer Part Number
LM3S5652
Description
Lm3s5652 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5652.pdf
(703 pages)
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Reset
Reset
Type
Type
DMA Channel Wait on Request Status (DMAWAITSTAT)
Base 0x400F.F000
Offset 0x010
Type RO, reset 0x0000.0000
June 02, 2008
Bit/Field
31:0
RO
RO
31
15
0
0
RO
RO
Register 8: DMA Channel Wait on Request Status (DMAWAITSTAT), offset
0x010
This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can
pull this Low to hold off the μDMA from performing a single request until the peripheral is ready for
a burst request. The use of this feature is dependent on the design of the peripheral and is used to
enhance performance of the μDMA with that peripheral. You cannot read this register when the
controller is in the reset state.
30
14
0
0
WAITREQ[n]
RO
RO
29
13
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
Preliminary
RO
RO
24
WAITREQ[n]
WAITREQ[n]
0
8
0
Description
Channel [n] Wait Status
Channel wait on request status. For each channel 0 through 31, a 1 in
the corresponding bit field indicates that the channel is waiting on a
request.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S5652 Microcontroller
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
213
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