LM3S818 Luminary Micro, Inc, LM3S818 Datasheet - Page 359
LM3S818
Manufacturer Part Number
LM3S818
Description
Lm3s818 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S818.pdf
(392 pages)
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- Current page: 359 of 392
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February 6, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
QEI Interrupt Status and Clear (QEIISC)
Offset 0x028
3
2
1
0
RO
RO
31
15
0
0
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits
set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in
question has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the
corresponding interrupt reason.
RO
RO
30
14
0
0
reserved
IntTimer
IntIndex
IntError
Name
IntDir
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
9
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Indicates that a phase error was detected.
Indicates that the direction has changed.
Indicates that the velocity timer has expired.
Indicates that the index pulse has occurred.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
IntError
R/W1C
RO
19
0
3
0
LM3S818 Data Sheet
IntDir
R/W1C
RO
18
0
2
0
IntTimer
R/W1C
RO
17
0
1
0
IntIndex
R/W1C
RO
16
0
0
0
359
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