LM3S818 Luminary Micro, Inc, LM3S818 Datasheet - Page 268

• Manufacturer Part Number: LM3S818
• Description: Lm3s818 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI)
13.2.4.2
13.2.4.3
268
In this mode, SSICLK and SSIFSS are forced Low, and the transmit data line SSITX is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFSS is
pulsed High for one SSICLK period. The value to be transmitted is also transferred from the
transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSICLK,
the MSB of the 4 to 16-bit data frame is shifted out on the SSITX pin. Likewise, the MSB of the
received data is shifted onto the SSIRX pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSICLK. The received data is transferred from the serial shifter to the
receive FIFO on the first rising edge of SSICLK after the LSB has been latched.
Figure 13-3 shows the Texas Instruments synchronous serial frame format when back-to-back
frames are transmitted.
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer)
Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFSS signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSICLK signal are programmable through the SPO and SPH bits within the SSISCR0 control
register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the
SSICLK pin. If the SPO bit is High, a steady state High value is placed on the SSICLK pin when
data is not being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock
transition before the first data capture edge. When the SPH phase control bit is Low, data is
captured on the first clock edge transition. If the SPH bit is High, data is captured on the second
clock edge transition.
Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 13-4 and Figure 13-5.
SSITx/SSIRx
SSIClk
SSIFss
Preliminary
MSB
4 to 16 bits
LSB
February 6, 2007