AN2502 Freescale Semiconductor / Motorola, AN2502 Datasheet - Page 38

• Manufacturer Part Number: AN2502
• Description: Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
• Manufacturer: Freescale Semiconductor / Motorola

AN2502/D
Enhanced Mode
Code Listing
;**********************************************************************
;* SCI ENHANCED.ASM
;**********************************************************************
;* A software interrupt driven SCI module using two TIM channels for
;* the HC08 MCU. Enhanced mode.
;*
;* By Jorge Zambada
;* Motorola SPS
;* Mexico Applications Laboratory
;* Guadalajara, Mexico
;* 2003
;**********************************************************************
;* NOTES:
;**********************************************************************
;* 1) In this code listing we use one of the low cost family of the
;* HC08, the JK3 MCU. This MCU has two TIM channels, we use one for
;* transmission, and the other for reception. In this example we use
;* CH1 for transmission and CH0 for reception.
;* 2) In the SCISend,we start a transmission of the data stored in the*
;* transmission register rSCTDRL for 8 bit transmissions, and in
;* rSCTDRH:rSCTDRL for 9 bit transmissions. In RXTX_config are
;* configured the two channels for the two processes: reception and
;* transmission.
;* 3) Two different ISR (one for reception and one for transmission)
;* makes possible the full duplex operation of this software SCI
;* module.
;* 4) Bit times are calculated with a free running timer (TIM).
;* 5) A list of standard baud rates is shown below. Remember that the *
;* maximum baud rate is proportional to the input clock frequency of
;* the TIM.
;* 6) Two subroutines are provided for Transmitter empty and Receiver *
;* full if enabled in the configuration register, rSCCR.
;* 7) Three flags in the rSCSR make possible error detection:
;* ORE -> Receive overrun error. Is set when SCI Receiver Full SCRF
;* flag is set and a new reception is beginning.
;* PE -> Receive parity error. Is set when a received parity bit
;* is not equal to the parity calculation.
;* FE -> Framing error. Is set when receiving a logic '0' in the
;* stop bit reception.
;**********************************************************************
VectorStart EQU
; For TIM Prescaler of 1
; (Bus Freq)/(Baud Rate)=BITHI:BITLO ->1 bit time
; BITHI:BITLO * 1.3-31=BIT1HI:BIT1LO->1.3 bit time - pin check latency
; Example of 9600 bps, XTAL = 9.8304 MHz -> Bus Freq = 9.8304 MHz/4
; BITHI:BITLO = 2457600/9600 = $0100
; BIT1HI:BIT1LO = $0100*1.3 - 31 = $012E
;9600 baud
BITHI
38
EQU
Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
$FFDE
$01
Freescale Semiconductor, Inc.
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