AN2502 Freescale Semiconductor / Motorola, AN2502 Datasheet - Page 12

• Manufacturer Part Number: AN2502
• Description: Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
• Manufacturer: Freescale Semiconductor / Motorola

AN2502/D
Reception in
Enhanced Mode
12
Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
Steps 1 and 2 are the same in normal mode and enhanced mode:
Steps 3 through 6 are specific to enhanced mode:
The number of data bits received is dependent on the
rSCCR.
After a bit is shifted into the reception shift register, the received bit is
considered for the parity bit computation.
the parity bit is sent, if PEN is enabled
1. Reception of the start bit
2. Data bits reception process
3. Number of data bits to be received
4. Parity bit computation after each bit reception
5. One or two stop bit receptions
6. Subroutine for end of reception is executed if enabled in the
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IN THE LAST BIT TRANSMISSION,
THE CHANNEL IS CONFIGURED AS
CLEAR ON OUTPUT COMPARE
TO SEND STOP BIT.
Table 1. M — Data Length Configuration Bit
Figure 22. Stop Bit Transmission
1 BIT-TIME
DATA BIT
LAST
M
0
1
(PEN
AFTER THE STOP BIT IS SENT,
THE CHANNEL IS TURNED OFF
IF SCTE FLAG IS CLEAR.
Data Bits
Figure 23
IF SCTE IS SET, THE CHANNEL IS
CONFIGURED AS
CLEAR ON OUTPUT COMPARE
TO SEND THE NEXT START BIT.
STOP BIT
8
9
= 1).
shows the time at which
M
configuration bits in
MOTOROLA
rSCCR