AN2502 Freescale Semiconductor / Motorola, AN2502 Datasheet
AN2502
Related parts for AN2502
AN2502 Summary of contents
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... Freescale Semiconductor, Inc. Application Note AN2502/D 2/2004 Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI By Jorge Zambada Motorola SPS Mexico Applications Laboratory Guadalajara, Mexico Introduction This document describes how to use the HC08 Family’s 16-bit free-running timer and the timer interface module (TIM) to establish a full-duplex interrupt-driven software SCI module ...
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... Freescale Semiconductor, Inc. AN2502/D The time required for sending a byte is 10 bit-times. A bit-time is equal to 1/baud rate. For example, if the baud rate is 9600 bps, the entire frame takes 1.0416 ms. The transmission begins with a high-to-low transition as soon as the bus is in idle state; that is, in logic high for more than 10 bit-times. Next, the desired byte is transmitted with its least significant bit first ...
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... Two enable/disable bits for reception and/or transmission Bit RPF TPF SCRF SCTE = Unimplemented or Reserved Figure 2. SCI Status Register (rSCSR Reception is in progress 0 = Reception is not in progress 1 = Transmission is in progress 0 = Transmission not in progress Go to: www.freescale.com AN2502/D Modes Figure example of a pseudo Bit 0 3 ...
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... Freescale Semiconductor, Inc. AN2502/D SCRF — SCI Receiver Full SCTE — SCI Transmitter Empty Because this SCI performs full-duplex operation necessary to have four separate data registers; two for reception and two for transmission. Each SCI operation uses two data registers; one is used in the interrupt service routine to shift in data for reception and shift out data for transmission ...
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... Subroutine disabled for end of reception 1 = Two stop bits 0 = One stop bits 1 = Nine data bits 0 = Eight data bits 1 = Transmit enabled 0 = Transmit disabled 1 = Receive enabled 0 = Receive disabled 1 = Parity bit enabled 0 = Parity bit disabled 1 = Odd parity 0 = Even parity Go to: www.freescale.com AN2502/D Modes Bit 0 TEN REN PEN PTY 5 ...
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... Freescale Semiconductor, Inc. AN2502/D rSCSR1 Read: Write: SCRF — SCI Receiver Full Bit RPF — Receive in Progress Flag SCTE — SCI Transmitter Empty TPF — Transmit in Progress Flag ORE — Overrun Error Flag FE — Framing Error Flag PE — Parity Error Flag ...
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... Bit RS7 RS6 RS5 RS4 = Unimplemented or Reserved Bit Bit TD7 TD6 TD5 TD4 = Unimplemented or Reserved Go to: www.freescale.com AN2502/D Modes RD8 RD3 RD2 RD1 RD0 RS8 RS3 ...
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... Freescale Semiconductor, Inc. AN2502/D Read: Write: Read: Write: Figure 13. SCI Transmit Data Registers (rSCTSRH:rSCTSRL) The number of bits used in the data registers is configured in the character length selection bit (M) in rSCCR. Reception possible to implement full-duplex operation because two independent Normal Mode channels of the TIM are used for each of the operations with independent data registers ...
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... Figure 16. Time Added After the Start Bit shows that the time added to the reception channel between the first 0.3 BIT-TIME FIRST DATA BIT 1 BIT-TIME Figure 17. Data Bit Reception Go to: www.freescale.com 0.7 BIT-TIME FIRST 30 pin check + – bit-time latency SECOND DATA BIT AN2502/D Modes 9 ...
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... Freescale Semiconductor, Inc. AN2502/D As soon as the last bit is received, the received data message is moved from the reception register that is being shifted in each bit reception to a user-readable reception register. To complete a data reception, the reception channel is configured as input capture on falling edges to detect the start bit of the next data message to be received ...
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... Figure 20. First Data Bit Transmission 1 BIT-TIME FIRST SECOND DATA BIT DATA BIT Figure 21. Data Bits Transmission Figure 21, each bit to be transmitted is shifted out of the SCTE flag is checked before turning off the channel to: www.freescale.com AN2502/D Modes FIRST DATA BIT Figure 22. As shown in this 11 ...
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... Freescale Semiconductor, Inc. AN2502/D Reception in Steps 1 and 2 are the same in normal mode and enhanced mode: Enhanced Mode 1. Reception of the start bit 2. Data bits reception process Steps 3 through 6 are specific to enhanced mode: 3. Number of data bits to be received 4. Parity bit computation after each bit reception 5 ...
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... PE = RPTY ⊕ PTY summarizes the parity error combinations. Table 3. Parity Error Truth Table PEN PTY to: www.freescale.com AN2502/D Modes PARITY BIT PE flag is set PTY configuration bit in the No parity Odd parity Even parity Parity Error No error Error No error ...
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... Freescale Semiconductor, Inc. AN2502/D In enhanced mode software SCI, one or two more output compare interrupts are performed to check whether the stop bits are at a proper level. Depending on the either one or two output compares low level is detected in the reception of the stop bits, a framing error is set in the ...
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... Figure 25. Data Bit Transmission in Enhanced Mode (PEN = 1), the parity bit is sent after the last data bit TPTY = Data bit (0) ⊕ Data bit (1) ⊕ … ⊕ Data bit (N-1) Parity bit to be transmitted = (TPTY ⊕ PTY) Go to: www.freescale.com AN2502/D Modes rSCCR SECOND DATA BIT 15 ...
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... Freescale Semiconductor, Inc. AN2502/D Figure 25 After the parity bit is transmitted, one or two stop bits are transmitted depending on the 16 Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI Table 6. Parity Bit to be Transmitted (1) TPTY PTY TPTY bit is used for temporal computation of the parity bit ...
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... Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI For More Information On This Product, (TIEN = 1) in rSCCR. Table 8. Transmission Completed Subroutine Enable Bit TIEN Configuration 1 Subroutine enabled 0 Subroutine disabled RTI BRCLR SCR,rSCSR ;[.r...] : : : PSHH BCLR CH0F,TSC0 BRSET RPF,rSCSR,rxinprog ;[ CLC BRCLR RPIN,PTD,nocarry Go to: www.freescale.com AN2502/D Modes ;[9 due to interrupt entry] ;[2] ;[4] ;[1] ;[.r...] * 17 ...
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... Freescale Semiconductor, Inc. AN2502/D This code shows that the pin check latency is (0/+5) CPU bus cycles. In the code listings at the end of the document, the user can also find the duration of the instructions preformed prior to the pin check instruction for the enhanced mode. ...
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... Max Cycles Rx, Max Cycles Tx) Bus Go to: www.freescale.com AN2502/D Maximum Baud Rates Full-Duplex Bus Bus Bus 8 2.4576 8 MHz MHz MHz 90909.09 11170.91 36363.64 Full-Duplex ...
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... Freescale Semiconductor, Inc. AN2502/D Full-Duplex Maximum When receiving data in the full-duplex operation based on Baud Rate the input pin for the bit being received must be performed within 30% and 70 bit-time to check the state of the pin in the center. For full-duplex operation, the value of the bit-time multiplied by 0.4 (70% to 30%) in timer counts must be greater that the number of cycles for the transmission interrupt ...
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... For More Information On This Product, RXTX_config STOP AND RESET TIMER CH0 IC ON FALLING EDGES CH1 UNDER PORT CONTROL SET Tx PIN FOR IDLE STATE CLEAR RECEPTION FLAGS SET TRANSMITTER EMPTY FLAG ENABLE INTERRUPTS RUN TIMER RTS Figure 29. Initial Configuration — Normal Mode Go to: www.freescale.com AN2502/D Software 21 ...
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... Freescale Semiconductor, Inc. AN2502/D 22 Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI YES CH1 CLEAR ON OC Figure 30. SCI Send — Normal Mode For More Information On This Product, Go to: www.freescale.com SCISend CLEAR TRANSMITTER EMPTY FLAG TRANSMIT CHANNEL ACTIVE NO TCH1H:TCH1L = TCNTH:TCNTL + ...
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... ROR Tx SHIFT REGISTER YES CONFIGURE CH1 CARRY SET? AS SET CONFIGURE CH1 AS CLEAR ON OC RTI Figure 31. Transmit ISR — Normal Mode Go to: www.freescale.com AN2502/D Software CLEAR Tx IN PROGRESS FLAG YES Tx ER DISABLE CH1 IS EMPTY SHIFT REG = Tx DATA REG SET Tx EMPTY ...
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... Freescale Semiconductor, Inc. AN2502/D 24 Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI RX_ISR YES Rx IN COPY RPIN INTO PROGRESS? CARRY FLAG NO SET Rx IN ROR RECEPTION PROGRESS FLAG SHIFT REGISTER Rx SHIFT REG = CARRY SET? #0x80 SET NEXT OC PERIOD SET NEXT OC (1.3 BIT-TIME – ...
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... EQU $02 ;BITLO EQU $00 ;BIT1HI EQU $02 ;BIT1LO EQU $80 ;2400 baud MOTOROLA Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI For More Information On This Product, Go to: www.freescale.com AN2502/D Software * * * * * * * * * * * * * * * * * ...
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... Freescale Semiconductor, Inc. AN2502/D ;BITHI EQU $04 ;BITLO EQU $00 ;BIT1HI EQU $05 ;BIT1LO EQU $19 ;1200 baud ;BITHI EQU $08 ;BITLO EQU $00 ;BIT1HI EQU $0A ;BIT1LO EQU $4C ; MISC Flags TPIN EQU 5 RPIN EQU 4 ; Bit positions on the SCIFlag register RPF EQU 7 TPF EQU 6 SCRF EQU 5 SCTE EQU 4 ...
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... CYCLES of instruction ; prior to RX interrupt] ; Wait for byte to be received. This ; flag is set when the received byte is ; moved from the reception shift ; register to the reception data ; register. ; Store received byte in the accumulator Go to: www.freescale.com AN2502/D Software * * * * * * * * * ...
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... Freescale Semiconductor, Inc. AN2502/D BCLR SCRF,rSCSR RTS ;********************************************************************** ;* PutByte subroutine is a friendly usage of the SCI Transmission ;* features, which provides Flags check and storage from the ;* accumulator to the transmission register. User would modify this ;* subroutine if the byte to be sent is stored in another register location. ...
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... Set time for next OC ; after 1 bit time ; Store the calculated time in the ; channel register for next output ; compare ; With this operation, the bit transmitted is copied in the carry ; flag ; if Carry is High, the transmission ; channel is configured to set on Go to: www.freescale.com AN2502/D Software * * * * * * * * * ...
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... Freescale Semiconductor, Inc. AN2502/D oc_low: MOV #$58,TSC1 ; If carry cleared, config. PULH RTI oc_high: MOV #$5C,TSC1 ; If carry set, config. PULH RTI txinprog: LDA rSCTSR CBEQA #$00,txfinished LDHX TCH1H TXA ADD #BITLO TAX PSHH PULA ADC #BITHI PSHA PULH STHX TCH1H CLC ROR ...
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... Store $80 which represents a stop bit ; after 8 transmission bits. ; Since this is the first time we enter ; the ISR for the reception, a 1.3 bit ; time minus pin check latency must be ; added to the channel register. ; Add 1.3 bit time minus pin check lat. Go to: www.freescale.com AN2502/D Software * * * * * * ...
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... Freescale Semiconductor, Inc. AN2502/D PSHA PULH STHX TCH0H MOV #$50,TSC0 ; config. channel 0 as output PULH RTI rxinprog: CLC BRCLR RPIN,PTD,nocarry SEC nocarry: ROR rSCRSR BCS rxfinished LDHX TCH0H TXA ADD #BITLO TAX PSHH PULA ADC #BITHI PSHA PULH STHX TCH0H MOV #$50,TSC0 ...
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... Vector Assigned $FFF8-$FFF9) FDB dummy_isr ; ~IRQ1 FDB dummy_isr ; SWI Vector FDB Start MOTOROLA Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI For More Information On This Product, ; return ; TIM1 Channel 1 Vector ; TIM1 Channel 0 Vector ; Reset Vector Go to: www.freescale.com AN2502/D Software * * 33 ...
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... Freescale Semiconductor, Inc. AN2502/D Enhanced Mode Flowcharts 34 Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI RXTX_config STOP AND RESET TIMER CH0 IC ON FALLING EDGES CH1 UNDER PORT CONTROL SET Tx PIN FOR IDLE STATE CLEAR RECEPTION FLAGS SET Tx EMPTY FLAG ...
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... END OF TX DEPENDING ON M SET TRANSMITTER EMPTY FLAG YES ADD 1 BIT-TIME CHANNEL NO ADD 1 BIT-TIME TO Tx CHANNEL CLEAR Tx STATUS FLAGS IN STATUS REGISTER 2 CONFIGURE CH1 AS CLEAR SEND START BIT RTS Figure 34. SCI Send — Enhanced Mode Go to: www.freescale.com AN2502/D Software 35 ...
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... Freescale Semiconductor, Inc. AN2502/D TX_ISR Tx IN PROGRESS? NO SET Tx IN PROGRESS FLAG SET TIME FOR NEXT OC (1 BIT-TIME) CLEAR CARRY ROR SCTSRH:SCTSRL 1 YES CARRY SET? NO CONFIGURE CH1 CONFIGURE CH1 AS SET CLEAR ON OC TOGGLE RTI TEMPORAL PARITY Figure 35. Transmit ISR — Enhanced Mode ...
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... SET NEXT OC PERIOD (1 BIT-TIME) CONFIG CH0 AS OC WITH PIN UNDER PORT CONTROL RTI NO YES YOUR CODE RIEN = 1? HERE CONFIG CH0 FALLING EDGES Go to: www.freescale.com AN2502/D Software ROR SCRSRH:SCRSRL NO CARRY SET? YES FE < PTYRX <- 1 STBRX <- 0 PTYRX = AND ...
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... Freescale Semiconductor, Inc. AN2502/D Enhanced Mode Code Listing ;********************************************************************** ;* SCI ENHANCED.ASM ;********************************************************************** ;* A software interrupt driven SCI module using two TIM channels for ;* the HC08 MCU. Enhanced mode Jorge Zambada ;* Motorola SPS ;* Mexico Applications Laboratory ;* Guadalajara, Mexico ;* 2003 ;********************************************************************** ;* NOTES: ;********************************************************************** ;* 1) In this code listing we use one of the low cost family of the ...
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... Receive Enable ; Parity Enable ; Parity Bit ; Receive Data Register Full ; Receive in progress ; Transmit Data Register Empty ; Transmit in progress ; Overrun Error ; Framing Error ; Parity Error ; Sending PTY ; sending STB ; Receiving PTY ; Receiving STB ; Temporal Tx Parity bit ; Temporal Rx Parity bit Go to: www.freescale.com AN2502/D Software 39 ...
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... Freescale Semiconductor, Inc. AN2502/D ; Include file for the 68HC908JL3, 68HC908JK3, 68HC908JK1 Include 'jk3_registers.inc' ORG RamStart rSCCR RMB 1 rSCSR1 RMB 1 rSCSR2 RMB 1 rSCRDRH RMB 1 rSCRDRL RMB 1 rSCRSRH RMB 1 rSCRSRL RMB 1 rSCTDRH RMB 1 rSCTDRL RMB 1 rSCTSRH RMB 1 rSCTSRL RMB 1 ORG RomStart ;********************************************************************** ;* Program goes here after reset ...
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... Wait for byte to be received. This ; flag is set when the received byte is ; moved from the reception shift ; register to the reception data ; register. ; Store received byte in the H:X ; registers ; Clear receiver full flag to allow ; more receptions Go to: www.freescale.com AN2502/D Software * * * * * * * * ...
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... Freescale Semiconductor, Inc. AN2502/D ;********************************************************************** ;* PutByte subroutine is a friendly usage of the SCI Transmission ;* features, which provides Flags check and storage from the H:X ;* registers to the transmission register. User would modify this ;* subroutine if the byte to be sent is stored in another register location. ;********************************************************************** PutByte: STHX rSCTDRH ...
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... This bit position depends on the ; data bits length ; 09 BIT SELECTION ; Set bit to indicate end of data ; bits reception ; Clear Channel Flag ; indicating that a new data transmitted can be queued. ; Read current count ; Add 1 bit time for next compare ; to send start bit Go to: www.freescale.com AN2502/D Software 43 ...
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... Freescale Semiconductor, Inc. AN2502/D BRCLR SB,rSCCR,storeinCH1 TXA ADD #BITLO TAX PSHH PULA ADC #BITHI PSHA PULH storeinCH1: STHX TCH1H LDA rSCSR2 AND #$0D STA rSCSR2 MOV #$58,TSC1 SCIsend_end: RTS ;********************************************************************** ;* This ISR is dedicated only for transmission. each transmitted bit ;* generate this interrupt, excluding the second stop bit when ...
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... Check if sending parity ; Check if sending stop bits ; transmitting data bits ; Copy CCR into transmit data register ; zero, data transmission ; is done ; Exit from interrupt ; send next bit depending on carry ; Add 1 bit time for next output ; compare Go to: www.freescale.com AN2502/D Software 45 ...
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... Freescale Semiconductor, Inc. AN2502/D TAX PSHH PULA ADC #BITHI PSHA PULH STHX TCH1H PULA TAP BRA oc_highorlow txfinished: BRCLR PEN,rSCCR,sendingPTY BSET PTYTX,rSCSR2 BCLR STBTX,rSCSR2 LDA rSCCR AND #$01 LSLA EOR rSCSR2 COMA LSRA LSRA TPA BRA nextbittime ; Calc. next OC time sendingPTY: BSET ...
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... Add 1 bit time for next compare ; Add 1 more bit time ; for next compare ; to handle 2 stop bits of the current ; data being sent ; Store calculated data into the ; channel register ; Reset Flags for next transmission ; Clear TX Flags in rSCSR2 ; config. channel to: www.freescale.com AN2502/D Software 47 ...
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... Freescale Semiconductor, Inc. AN2502/D BRA TxPending NoTxPending: CLR TSC1 TxPending: PULH BRCLR TIEN,rSCCR,EXITTX JMP SCITXEMPTY EXITTX: RTI ;********************************************************************** ;* This ISR is dedicated for reception. ;* When the receiving line is in idle state, this channel is ;* configured as input capture on falling edge, waiting for a start ;* bit. When the start bit is received, the channel is configured as ...
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... Pin under port control. Each output ; compare interrupt will give the time ; to check the pin state, that is why ; the channel is configured as pin ; under port control ; Return from interrupt ; 7........ [1 CYCLES] Go to: www.freescale.com AN2502/D Software 49 ...
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... Freescale Semiconductor, Inc. AN2502/D BRCLR RPIN,PTD,nocarry SEC nocarry: TPA PSHA LDA rSCSR2 AND #%00001100 CBEQA #%00001000,ptyrec CBEQA #%00000100,sb1rec CBEQA #%00001100,sb2rec ; Program goes here if receiving data bits BCC notogPTY LDA rSCSR2 EOR #$01 STA rSCSR2 notogPTY: PULA TAP ROR rSCRSRH ROR rSCRSRL BCC ...
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... Branch to 2nd Stop Bit reception if ; SB=0 ; Pop CCR and store it in the acc. ; Calculate Framing Error ; flag ; (A.1 = 1)? -> FE=1 ; ELSE -> FE=0 ; Indicate that the next received bit ; is the second stop bit ; Calculate next output compare time ; If FE=1, rx done ; Calculate Framing Error Go to: www.freescale.com AN2502/D Software 51 ...
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... Freescale Semiconductor, Inc. AN2502/D AND #$02 BCLR FE,rSCSR1 ORA rSCSR1 STA rSCSR1 rxfinished: LDA rSCRSRH LDX rSCRSRL CLC adjustdata: RORA RORX BCC adjustdata BCLR ORE,rSCSR1 BRCLR SCRF,rSCSR1,noORerror BSET ORE,rSCSR1 noORerror: STA rSCRDRH STX rSCRDRL BCLR RPF,rSCSR1 BSET SCRF,rSCSR1 ; valid data on rSCRDRH:rSCRDRL MOV ...
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... Vector Assigned $FFE8-$FFE9) ; (No Vector Assigned $FFEA-$FFEB) ; (No Vector Assigned $FFEC-$FFED) ; (No Vector Assigned $FFEE-$FFEF) ; (No Vector Assigned $FFF0-$FFF1) ; TIM1 Overflow Vector ; TIM1 Channel 1 Vector ; TIM1 Channel 0 Vector ; (No Vector Assigned $FFF8-$FFF9) ; ~IRQ1 ; SWI Vector ; Reset Vector Go to: www.freescale.com AN2502/D Software * * 53 ...
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... Freescale Semiconductor, Inc. AN2502/D Conclusion In this application note, two modes of software SCI are described and coded. One is for a simple asynchronous communication protocol, where no data length selection is available and no errors are detected. The other implementation of the SCI is for a multiple format with error detection asynchronous protocol ...
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... Freescale Semiconductor, Inc. MOTOROLA Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI For More Information On This Product, Go to: www.freescale.com AN2502/D 55 ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2004 AN2502/D Go to: www.freescale.com ...