AN2491 Freescale Semiconductor / Motorola, AN2491 Datasheet - Page 8

• Manufacturer Part Number: AN2491
• Description: Simplified Mnemonics for PowerPC Instructions
• Manufacturer: Freescale Semiconductor / Motorola

Branch Instruction Simplified Mnemonics
Branch Instruction Simplified Mnemonics
Integer record-form instructions update CR0 and floating-point record-form instructions update CR1, as
described in Table 7.
4.4.1.1 Specifying a CR Bit
Note that the AIM version of the PowerPC architecture numbers CR bits 0–31 and Book E numbers them
32–63. However, no adjustment is necessary to the code; in Book E devices, 32 is automatically added to
the BI value, as shown in Table 7 and Table 8.
Some simplified mnemonics incorporate only the BO field (as described Section 4.2, “Eliminating the BO
Operand”). If one of these simplified mnemonics is used and the CR must be accessed, the BI operand can
be specified either as a numeric value or by using the symbols in Table 8.
Compare word instructions (described in Section 5, “Compare Word Simplified Mnemonics”),
floating-point compare instructions, move to CR instructions, and others can also modify CR fields, so CR0
and CR1 may hold values that do not adhere to the meanings described in Table 7. CR logical instructions,
described in Section 6, “Condition Register Logical Simplified Mnemonics,” can update individual CR bits.
8
(branch if true) and BO = 4 branch if false)
conditions but not CTR values—BO = 12
CRn Bit
CR0[0]
CR0[1]
CR0[2]
CR0[3]
CR1[0]
CR1[1]
CR1[2]
CR1[3]
simplified mnemonics based on CTR
Simplified mnemonics based on CR
Table 7. CR0 and CR1 Fields as Updated by Integer and Floating-Point Instructions
Standard branch mnemonics and
AIM
0
1
2
3
4
5
6
7
CR Bits
Book E 0–2 3–4
32
33
34
35
36
37
38
39
Figure 3. BI Field (Bits 11–14 of the Instruction Encoding)
Simplified Mnemonics for PowerPC™ Instructions
Freescale Semiconductor, Inc.
000
000
000
000
001
001
001
001
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BI
00 Negative (LT)—Set when the result is negative.
01 Positive (GT)—Set when the result is positive (and not zero).
10 Zero (EQ)—Set when the result is zero.
11 Summary overflow (SO). Copy of XER[SO] at the instruction’s completion.
00 Copy of FPSCR[FX] at the instruction’s completion.
01 Copy of FPSCR[FEX] at the instruction’s completion.
10 Copy of FPSCR[VX] at the instruction’s completion.
11 Copy of FPSCR[OX] at the instruction’s completion.
values
BI[0–2] specifies CR field, CR0–CR7. BI[3–4] specifies one of the
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The BI operand specifies the entire 5-bit field. If CR0 is used,
the bit can be identified by LT, GT, EQ, or SO. If CR1–CR7 are
used, the form 4 * crS + LT|GT|EQ|SO can be used.
reduced BI operand (crS)
Specified by a separate,
BI Opcode Field
0
Description
1
2
Incorporated into the simplified
mnemonic.
3
4 bits in a CR field. (LT, GT, EQ, SO)
4
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