AN2491 Freescale Semiconductor / Motorola, AN2491 Datasheet - Page 15

• Manufacturer Part Number: AN2491
• Description: Simplified Mnemonics for PowerPC Instructions
• Manufacturer: Freescale Semiconductor / Motorola

Table 18 shows the simplified branch mnemonics incorporating conditions.
Instructions using the mnemonics in Table 18 indicate the condition bit, but not the CR field. If no field is
specified, CR0 is used. The CR field symbols defined in Table 9 (cr0–cr7) are used for this operand, as
shown in examples 2–4 of Section 4.6.1, “Branch Simplified Mnemonics that Incorporate CR Conditions:
Examples,” below.
4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions:
The following examples use the simplified mnemonics shown in Table 18:
MOTOROLA
1
2
Branch
Branch Conditional
Branch Conditional to Link Register
Branch Conditional to Count Register
x stands for one of the symbols in Table 16, where applicable.
BI can be a numeric value or an expression as shown in Table 9.
Branch if less than
Branch if less than or equal
Branch if equal
Branch if greater than or equal
Branch if greater than
Branch if not less than
Branch if not equal
Branch if not greater than
Branch if summary overflow
Branch if not summary overflow
Branch if unordered
Branch if not unordered
1. Branch if CR0 reflects not-equal condition.
2. Same as (1) but condition is in CR3.
Table 17. Branch Instructions and Simplified Mnemonics that Incorporate CR Conditions
bne target
bne cr3,target
Branch Semantics
Examples
Instruction
Table 18. Simplified Mnemonics with Comparison Conditions
Simplified Mnemonics for PowerPC™ Instructions
Freescale Semiconductor, Inc.
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bng
bun
bnu
beq
bge
bne
bso
bns
bgt
bc (bca bcl bcla) BO,BI,target_addr bx
ble
bnl
bc
blt
bcctr (bcctrl)
b (ba bl bla)
Mnemonic
bclr (bclrl)
LR Update Not Enabled
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Standard
equivalent to
equivalent to
beqa
bgea
bnea
bnga
bsoa
bnsa
buna
bnua
blea
bgta
bnla
blta
bca
beqlr beqctr
bgelr bgectr
bnelr bnectr
bnglr bngctr
bsolr bsoctr
bnslr bnsctr
bunlr bunctr
bnulr bnuctr
blelr
bgtlr
bnllr
bclr
bltlr
target_addr
Syntax
BO,BI
BO,BI
blectr
bgtctr
bnlctr
bltctr
bcctr
Branch Instruction Simplified Mnemonics
bngl
bunl
bnul
beql
bgel
bnel
bsol
bnsl
bgtl
bnll
blel
bcl
bltl
bxctr (bxctrl)
bc 4,2,target
bc 4,14,target
1
Mnemonic
Simplified
bxlr (bxlrl)
(bxa bxl bxla)
LR Update Enabled
beqla
bgela
bnela
bngla
bsola
bnsla
bunla
bnula
bgtla
bnlla
blela
bltla
bcla
—
bnglrl bngctrl
bunlrl bunctrl
bnulrl bnuctrl
beqlrl beqctrl
bgelrl bgectrl
bnelrl bnectrl
bsolrl bsoctrl
bnslrl bnsctrl
bgtlrl bgtctrl
blelrl
bnllrl bnlctrl
crS
bclrl
bltlrl
2
Syntax
,target_addr
crS
crS
blectrl
bltctrl
bcctrl
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