CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 3

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
Pin Description
Note:
11
21
6
8
25
28
27
26
45
46
5
51
16
55
50
22
23
34,40
9
13
54
33,39
19
47
24
2.
Pin
PU = internal Pull-up. PD = internal Pull-down. Typically = 250 kW (range 200 kW to 500 kW).
SELSDR_DDR#/PCI
1
FS2/24_48M
AGP0
AGP2
IREF
SDATA
SCLK
PD#/SRESET#
BUF_IN
FBOUT
VDDAGP
VDDC
VDDPCI
VDDR
VDDI
VDD48M
VDD
VDDD
VSSAGP
VSSPCI
VSSC
VSSD
VSS48M
VSSI
VSS
Name
[2]
(continued)
VDD48M I/O
VDDPCI
VDDAG
VDDAG
PWR
P
P
PD
PD
PU
I/O
I/O
I/O Serial Data Input. Conforms to the Philips I2C specification of a Slave
I/O
O
O
I
I
Power-on Bidirectional Input/Output. At power-up, SELSDR_DDR is the
input. When the power supply voltage crosses the input threshold voltage,
SELSDR_DDR state is latched and this pin becomes PCI clock
output.SelSDR_DDR#. = 0, DDR Mode. SelSDR_DDR#. = 1, SDR Mode.
Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When
the power supply voltage crosses the input threshold voltage, FS2 state is
latched and this pin becomes 24_48M, a SIO programmable clock output.
AGP Clock Output. Is synchronous to CPU clocks. See Table 1.
AGP Clock Output. Is synchronous to CPU clocks. See Table 1.
Current reference programming input for CPU buffers. A precise resistor is
attached to this pin, which is connected to the internal current reference.
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
Serial Clock Input. Conforms to the Philips I2C specification.
Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0, this pin
becomes a SRESET# open drain output, and the internal pulled up is not active.
See system reset description. If Byte6 Bit7 = 1 (default), this pin becomes PD#
input with an internal pull-up. When PD# is asserted LOW, the device enters
power-down mode. See power management function.
If SelSDR_DDR#.= 0, 2.5V CMOS type input to the DDR differential buffers.If
SelSDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer.
If SelSDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the DDRT(0:5) signals.If
SelSDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the SDRAM(0:11) signals
3.3V Power Supply for AGP clocks
3.3V Power Supply for CPUT/C clocks
3.3V Power Supply for PCI clocks
3.3V Power Supply for REF clock
2.5V Power Supply for CPUCS_T/C clocks
3.3V Power Supply for 48M
3.3V Common Power Supply
If SelSDR_DDR#.= 0, 2.5V Power Supply for DDR clocksIf SelSDR_DDR#.=
1, 3.3V Power Supply for SDR clocks.
Ground for AGP clocks
Ground for PCI clocks
Ground for CPUT/C clocks
Ground for DDR clocks
Ground for 48M clock
Ground for ICPUCS_T/C clocks
Common Ground
Description
CY28341
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