CY28341 Cypress Semiconductor, CY28341 Datasheet
CY28341
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CY28341 Summary of contents
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... VDDPCI PCI(3:6) **SELSDR_DDR/PCI1 *MULTSEL/PCI2 PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:2) VDD48M **FS2/24_48M 48M / 2 24_48M *PD#/SRESET# SRESET# VDDD FBOUT DDRT(0:5)/SDRAM(0,2,4,6,8,10) DDRC(0:5)/SDRAM(1,3,5,7,9,11) • 3901 North First Street • CY28341 DDR Systems CPU AGP 66.80 66.80 100.00 66.80 120.00 60.00 133.33 66.67 72.00 72.00 105.00 70.00 160.00 64.00 140.00 70.00 77.00 77.00 110.00 73.33 180.00 60 ...
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... FS1 state is latched and this pin becomes PCI_F clock output. Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When PD the power supply voltage crosses the input threshold voltage, FS3 state is latched and this pin becomes 48M, a USB clock output. CY28341 Description . IN Page ...
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... If SelSDR_DDR#.= 0, 2.5V Power Supply for DDR clocksIf SelSDR_DDR#.= 1, 3.3V Power Supply for SDR clocks. Ground for AGP clocks Ground for PCI clocks Ground for CPUT/C clocks Ground for DDR clocks Ground for 48M clock Ground for ICPUCS_T/C clocks Common Ground CY28341 Description Page ...
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... Read 29 Acknowledge from slave 30:37 Byte count from slave – 8 bits 38 Acknowledge 39:46 Data byte from slave – 8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop CY28341 Page ...
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... In K7 mode, this bit is ignored.In P4 mode when PD# asserted LOW, CPUT stops in a HIGH state, CPUC stops in a LOW state mode when PD# asserted LOW, CPUT and CPUC stop in High-Z. Only For reading the hardware setting of the Pin11 MULT0 value. CY28341 Byte Read Protocol Description Start Slave address – ...
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... See Table output enabled (running output disabled asynchronously in a LOW state output enabled (running output disabled asynchronously in a LOW state output enabled (running output disabled asynchronously in a LOW state. Description Frequency Selection Default CY28341 Description AGP(0:2) Skew Shift Default –280 ps +280 ps ...
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... LOW state. Description WD1 WD0 0 0 Off second seconds seconds seconds seconds seconds seconds seconds seconds seconds seconds seconds seconds seconds seconds CY28341 Description FUNCTION Page ...
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... Revision ID bit [3] Revision ID bit [2] Revision ID bit [1] Revision ID bit [0] Cypress Vender ID bit [3]. Cypress Vender ID bit [2]. Cypress Vender ID bit [1]. Cypress Vender ID bit [0]. Description Table 8. XXXXX Spread Spectrum Clock Generation (SSCG) Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 7. CY28341 Description Description FS(4:0) P 96016000 Page ...
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... ’ ’ 0 ’ Figure 1. when the chip was not powered down. On power-up, the VCOs will stabilize to the correct pulse widths within about 0.5 mS. CY28341 until the BIOS clears ...
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... 10.0 500 9.85 10.2 7.35 175 700 175 20% 125 0 200 0 –150 +150 –150 CY28341 and V should be constrained to the range: IN OUT < OUT 2.5V ± 5%, T DDI DD A Min. Typ. 2.0 2.2 0 [5] 150 [5] 175 ...
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... CY28341 200 MHz [4] Min. Max Unit Notes 280 430 11,14,21 4.85 5.1 nS 11,14,21 175 467 ps 13,15,25 0 200 0 11,15,21 –200 +200 ps 11,15,21 510 760 mV 26 325 ps 24,31 45 ...
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... DD DDD DDD DDD – 0.2 0.2 – 0.2 + 0.2 0 0.6 0.7 V DDD DDD 0 9.85 10.2 14.85 15 100 100 ±75 ±75 ±100 ±100 100 100 3 3 CY28341 200 MHz Min. Max Unit Notes 1.0 4.0 ns 11,13 500 ps 11,14, 7,11,14 41.660 41.667 ns 7,11,14 1.0 4.0 ns 11,13 500 ps 11,14, 7,11,14 69.8413 71.0 ns 7,11,14 1.0 4.0 ns 11,13 1000 ps 11,14,15 0.5*V 0.5 ...
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... CPU = 133 MHz, this diagram and description is appli- cable for all valid CPU frequencies 66, 100, 133, 200MHz.Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. CY28341 Page ...
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... LOW state as soon as possible. When in power-down (and before power is removed), all outputs are synchronously stopped in a LOW state (see figure3 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I2C function is also disabled. CY28341 Page ...
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... 133M 33M 66M 48M 14.318M 133M 133M 133M H z Figure 4. Power-down Assertion Timing Waveform (in K7 Mode) Document #: 38-07367 Rev. *A CY28341 Page ...
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... This time diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power-up. After the first HIGH to LOW transition of VTT_PWRGD#, device is not affected, VTT_PWRGD# is ignored. Document #: 38-07367 Rev. *A order to guarantee a glitch-free operation, no partial clock pulses. < ait for Sam ple Sels Delay VTT_GD# State 1 State 2 On CY28341 State 3 (Note A) On [31] Page ...
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... Ohm VDDCPU(1.5V) Ohm 5" Ohm 1" 680 pF 60.4 Ohm 500 Ohm 3.3V Figure 8. 6” 6” Figure 9. CY28341 tio n Measurement Point 500 Ohm " ...
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... LB2 Figure 10. Group Timing Relationships and Tolerances 0 t CPUCS to CSAGP AGP t AGP to 3” PCI 63 470 221 w/mult0 = 0 CY28341 Max Load (in pF See Figure 10 See Figure 8 See Figure 9 CLK Measurement Point R tB1 CLK Measurement Point R C tB2 ...
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... Thin Shrunk Small Outline package (TSSOP) CY28341ZCT 56-pin Thin Shrunk Small Outline package (TSSOP)–Tape and Reel Document #: 38-07367 Rev. *A 10ns 20ns t CSAGP t AP Package Type CY28341 30ns Product Flow Commercial Commercial Commercial Commercial Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 56-lead Shrunk Small Outline Package O56 CY28341 51-85060-B 51-85062-C ...
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... Document Title: CY28341 Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems Document Number: 38-07367 Issue REV. ECN NO. Date ** 112783 05/28/02 *A 122908 12/26/02 Document #: 38-07367 Rev. *A Orig. of Change Description of Change DMG New Data Sheet RBI Add power requirements to maximum ratings information CY28341 Page ...