CY28341 Cypress Semiconductor, CY28341 Datasheet - Page 2

• Manufacturer Part Number: CY28341
• Description: Universal Single-Chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07367 Rev. *A
Pin Description
3
4
1
56
44,42,38,
36,32,30
43,41,37
35,31,29
7
12
53
52
48,49
14,15,17,
18
10
20
Pin
XIN
FS0/REF0
VTTPWRGD#
REF1
DDRT
(0:5)/SDRAM(0,2,4,6,
8,10)
DDRC
(0:5)/SDRAM(1,3,5,7,
9,11)
SELP4_K7 / AGP1
MULTSEL / PCI2
CPUT/CPUOD_T
CPUC/CPUOD_C
CPUCS_T/C
PCI (3:6)
FS1/PCI_F
FS3/48M
XOUT
Name
[2]
VDD48M I/O
VDDPCI
VDDPCI
VDDPCI
VDDAG
VDDR
VDDR
VDDD
VDDD
VDDC
VDDC
VDDI
PWR
VDD
VDD
P
PU
PU
PU
PD
PD
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at X
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
the power supply voltage crosses the input threshold voltage, FS0 state is
latched and this pin becomes REF0, buffered copy of signal applied at XIN.
If SELP4_K7 = 1, with a P4 processor setup as CPUT/C. At power-up,
VTT_PWRGD# is an input. When this input transitions to a logic LOW, the FS
(3:0) and MULTSEL are latched and all output clocks are enabled. After the
first HIGH to LOW transition on VTT_PWRGD#, this pin is ignored and will not
effect the behavior of the device thereafter. When the VTT_PWRGD# feature
is not used, please connect this signal to ground through a 10K resistor.
If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin
becomes REF1 and is a buffered copy of the signal applied at X
These pins are programmable through strapping pin11, SELSDR_DDR#.If
SELSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They
are “True” copies of signal applied at Pin45, BUF_IN. In this mode, VDDD must
be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase with)
signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V
These pins are programmable through strapping pin11, SELSDR_DDR#.If
SelSDR_DDR#.= 0, these pins are configured for DDR clock outputs. They are
“Complementary” copies of signal applied at Pin45, BUF_IN. In this mode,
VDDD must be 2.5VIf SelSDR_DDR#.= 1, these pins are configured for
SDRAM(1,3,5,7,9,11) single-ended clock outputs, copies of (and in phase with)
signal applied at Pin45, BUF_IN. In this mode, VDDD must be 3.3V.
Power-on Bidirectional Input/Output. At power-up, SELP4_K7 is the input.
When the power supply voltage crosses the input threshold voltage, SELP4_K7
state is latched and this pin becomes AGP1 clock output. SELP4_K7 = 1, P4
mode. SELP4_K7 = 0, K7 mode.
Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input.
When the power supply voltage crosses the input threshold voltage, MULTSEL
state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is
4 x IREFMULTSEL = 1, Ioh is 6 x IREF.
3.3V CPU Clock outputs. This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock
Output. See Table 1.
3.3V CPU Clock outputs. This pin is programmable through strapping pin7,
SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output.
If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock
Output. See Table 1.
2.5V CPU Clock Outputs for Chipset. See Table 1.
PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1.
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When
the power supply voltage crosses the input threshold voltage, FS1 state is
latched and this pin becomes PCI_F clock output.
Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When
the power supply voltage crosses the input threshold voltage, FS3 state is
latched and this pin becomes 48M, a USB clock output.
IN
.
Description
CY28341
IN
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