UPD78320GJ-5BJ NEC, UPD78320GJ-5BJ Datasheet - Page 21

• Manufacturer Part Number: UPD78320GJ-5BJ
• Description: 16/8-BIT SINGLE-CHIP MICROCONTROLLER
• Manufacturer: NEC

2.2.1
and modification of operand addressing. They consist of three 16-bit registers and one 8-bit register.
(1)
(2)
The control registers carry out dedicated functions such as control of the program sequence, status and stack memory,
incremented according to the number of bytes of the instruction to be fetched. If an instruction with data branch is
executed, immediate data and the register content are set. RESET input sets and branches the data of 0000H and 0001H
reset vector tables in the PC.
write access is carried out in units of the higher 8 bits (PSWH) or lower 8 bits (PSWL). Each flag can be manipulated
using the bit manipulation instruction. If an interrupt request is made or BRK instruction is executed, data is automatically
saved in the stack and is recovered by RETI or RETB instruction.
(a) Interrupt priority level transition flag (LT)
be manipulated by a program.
(b) Carry flag (CY)
into bit 7 or 15, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional
branch instruction.
(c) Zero flag (Z)
by the conditional branch instruction.
(d) Sign flag (S)
can be tested by the conditional branch instruction.
(e) Parity/overflow flag (P/V)
instruction, this flag is set to 1. In all other cases, it is reset to 0 (overflow flag operation).
is set to 1. If the bit number is odd, this flag is reset to 0 (parity flag operation).
This is a 16-bit register which holds the address information of the next program to be executed. It is normally
This is a 16-bit register consisting of various flags which are set or reset by the result of instruction execution. Read/
All bits are reset to 0 by RESET input.
This flag is used to control the interrupt priority. For normal operation of the interrupt control circuit, this bit must not
If a carry is generated out of bit 7 or 15 as a result of the execution of an operation instruction or a borrow is generated
When a bit manipulation instruction is executed, this flag functions as a bit accumulator.
When the operation result is zero, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested
When MSB of the operation result is “1”, this flag is set to 1. When the MSB is “0”, this flag is reset to 0. This flag
Only when an overflow or underflow occurs as two’s complement during execution of an arithmetic operation
If the bit number of the operation result set to 1 is even during execution of an logic operation instruction, this flag
This flag can be tested by the conditional branch instruction.
Control Register
Program counter (PC)
Program status word (PSW)
PSWH
PSWL
UF
7
7
S
RBS2 RBS1 RBS0
6
Z
6
Figure 2-3. PSW Format
RSS
5
5
AC
4
4
IE
3
0
3
P/V
2
0
2
LT
1
1
0
CY
0
0
0
PD78320, 78322
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