T35L6432A TM Technology Inc., T35L6432A Datasheet - Page 6

• Manufacturer Part Number: T35L6432A
• Description: 64k X 32 Sram 3.3v Supply, Fully Registered Inputs And Outputs, Burst Counter
• Manufacturer: TM Technology Inc.

tm
TRUTH TABLE
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Note: 1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one or
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
Snooze Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue
Burst
WRITE Cycle, Continue
Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
OPERATION
2.
3. All inputs except
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7.
more byte write enable signals
equals LOW. WRITE = H means all byte write signal are HIGH.
DQ17-DQ24.
of CLK.
required setup time plus High-Z time for
time.
of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
ADSP
BW1
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge
CH
TE
= enables write to DQ1-DQ8.
= LOW along with chip being selected always initiates an internal READ cycle at the L-H
BW4
ADDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
OE
None
None
None
None
None
None
USED
Next
Next
Next
Next
Next
Next
=enables write to DQ25-DQ32.
must meet setup and hold times around the rising edge ( LOW to HIGH)
CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
X
X
X
X
X
X
X
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
BW1
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
BW2
,
BW2
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
= enables write to DQ9-DQ16.
OE
P. 6
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
,
BW3
and staying HIGH throughout the input data hold
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
OE
or
BW4
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
must be HIGH before the input data
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
and
Publication Date: DEC. 1998
BWE
BW3
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
are LOW, or
T35L6432A
= enables write to
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H
L-H High-Z
L-H
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H
Revision:A
X
High-Z
GW
Q
D
Q
Q
Q
D
D
Q
Q
D
D