T35L6432A TM Technology Inc., T35L6432A Datasheet - Page 3

• Manufacturer Part Number: T35L6432A
• Description: 64k X 32 Sram 3.3v Supply, Fully Registered Inputs And Outputs, Burst Counter
• Manufacturer: TM Technology Inc.

tm
PIN DESCRIPTIONS
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
81, 82, 99, 100,
32-37, 44-49,
QFP PINS
93-96
87
88
89
98
92
97
86
83
84
85
CH
TE
ADSC
ADSP
SYM.
ADV
BWE
BW2 Synchronous a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9-
BW4
BW3
BW1
CLK
CE2
CE2
A15 Synchronous hold times around the rising edge of CLK. The burst counter -
GW
A0-
OE
CE
Synchronous the device. This input is sampled only when a new external address
Synchronous and must meet the setup and hold times around the rising edge of
Synchronous to occur independent of the BWE and BWn
Synchronous control and burst control inputs on its rising edge. All synchronous
Synchronous the device and conditions internal use of
Synchronous the device. This input is sampled only when a new external address
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
Synchronous being LOW, causes a new external address to be registered and a
Synchronous be deselected or selected along with new external address to be
TYPE
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input
Addresses: These inputs are registered and must meet the setup and
generates internal addresses associated with A0 and A1,during
burst cycle and wait cycle.
Byte Write: A byte write is LOW for a WRITE cyle and HIGH for
DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32.
Data I/O are high impedance if either of these inputs are LOW ,
conditioned by
Write Enable: This active LOW input gates byte write operations
CLK.
Global Write: This active LOW input allows a full 32-bit WRITE
the setup and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables, write
inputs must meet setup and hold times around the clock's rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
sampled only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
is loaded. This input can be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to enable
is loaded. This input can be used for memory depth expansion.
Output enable: This active LOW asynchronous input enables the
data output drivers.
Address Advance: This active LOW input is used to control the
(no address advance).
Address Status Processor: This active LOW input, along with
READ cycle is initiated using the new address.
Address Status Controller:This active LOW input causes device to
registered. A READ or WRITE cycle is initiated depending upon
write control inputs.
P. 3
BWE
being LOW.
DESCRIPTION
Publication Date: DEC. 1998
ADSP
. This input is
T35L6432A
lines and must meet
Revision:A
CE