T35L3232B TM Technology Inc., T35L3232B Datasheet

T35L3232B

Manufacturer Part Number

T35L3232B

Description

32k X 32 Sram Pipeline And Flow-through Burst Mode

Manufacturer

TM Technology Inc.

Datasheet

1.T35L3232B.pdf (19 pages)

Current page: 1 of 19
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SYNCHRONOUS

BURST SRAM

FEATURES

¡E FT pin for user configurable pipeline or

¡E Fast Access times:

¡ESingle 3.3V +0.3V/-0.165V power supply

¡ECommon data inputs and data outputs

¡EIndividual BYTE WRITE ENABLE and

¡E Three chip enables for depth expansion and

¡E Clock-controlled and registered address, data

¡EInternally self-timed WRITE CYCLE

¡EBurst control pins ( interleaved or linear burst

¡EHigh 30pF output drive capability at rated

¡ESNOOZE MODE for reduced power standby

¡E Burst Sequence :

OPTIONS

Part Number Examples

Taiwan Memory Technology, Inc. reserves the right

to change products or specifications without notice.

Pipeline

through

3-1-1-1

2-1-1-1

T35L3232B-3.8Q

T35L3232B-4T

PART NO.

Flow-

- Linear (MODE=GND)

- Interleaved (MODE=NC or VCC)

flow-through operation.

GLOBAL WRITE control

address pipelining

I/Os and control signals

sequence)

access time

MARKING

Package

- Pipeline – 3.8 / 4 / 4.5 ns

- Flow-through – 9 / 10 / 11ns

100-pin QFP

100-pin TQFP

Access

Cycle

time

10.5ns

3.8ns

6.6ns

9ns

-3.8

Pkg.

7.5ns

10ns

15ns

4ns

-4

4.5ns

8.5ns

11ns

15ns

-4.5

P. 1

32K x 32 SRAM

Pipeline and Flow-Through Burst Mode

GENERAL DESCRIPTION

Burst RAM family employs high-speed, low power

CMOS design using advanced triple-layer polysilicon,

double-layer metal technology. Each memory cell

consists of four transistors and two high valued resistors.

bits SRAM cells with advanced synchronous peripheral

circuitry and a 2-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled

by a positive-edge-triggered clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining

expansion chip enables (

inputs (

(

global write (

(

(MODE). The data outputs (Q), enabled by

also asynchronous.

either address status processor (

status controller (

addresses can be internally generated as controlled by

the burst advance pin (

to initiate self-timed WRITE cycle.

can be one to four bytes wide as controlled by the write

control inputs. Individual byte write

allows individual byte to be written.

DQ1-DQ8.

controls DQ17-DQ 24.

with

all bytes to be written.

capability allows written data available at the output for

the immediately next READ cycle. This device also

incorporates pipelined enable circuit for easy depth

expansion without penalizing system performance.

BW1

The Taiwan Memory Technology Synchronous

Addresses and chip enables are registered with

), Snooze enable (ZZ) and burst mode control

The T35L3232B SRAM integrates 32,768 x 32

Asynchronous inputs include the output enable

Address and write controls are registered on-chip

BWE

ADSC

BW2

Preliminary T35L3232B

being LOW.

BW2

BW3

ADSC

ADSP

BW3

ADV

chip enable (

controls DQ9-DQ16.

Publication Date: FEB. 2000

, and

CE2

BW4

) input pins. Subsequent burst

, and

BW4

and CE2), burst control

ADV

WRITE pass-through

controls DQ25-DQ32.

ADSP

, and

being LOW causes

can be active only

), write enables

WRITE cycles

BW1

Revision:0.A

BWE

) or address

), depth-

controls

), and

BW3

, are

Related parts for T35L3232B

T35L3232B Summary of contents

Page 1

... READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance Preliminary T35L3232B The T35L3232B SRAM integrates 32,768 x 32 chip enable ( CE2 and CE2), burst control ADSC ADSP ...

Page 2

... BYTE 4 BYTE 4 WRITE DRIVER 8 BYTE 3 BYTE 3 WRITE DRIVER 8 BYTE 2 BYTE 2 WRITE DRIVER 8 BYTE 1 BYTE 1 WRITE DRIVER ENABLE REGISTER P. 2 Preliminary T35L3232B OUTPUT 32K SENSE BUFFERS MEMORY AMPS ARRAY Publication Date: FEB. 2000 Revision:0 ¡ ...

Page 3

... P. 3 Preliminary T35L3232B ...

Page 4

... ADSS t ADSH A2 t AAS t AAH ADV suspends burst. t OEQ OEHZ t OELZ t KQX Q(A1) Q(A2) Q(A2+1) (NOTE1 Preliminary T35L3232B A3 Burst continued with new base address. Deselect cycle. Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Burst wraps around to its inital state. BURST READ DON' T CARE UNDEFINED Publication Date: FEB. 2000 Revision:0 ...

Page 5

... EHZ ( ( ( (NOTE Preliminary T35L3232B ( ( Q( und DON'T CARE UNDEFINED Publication Date: FEB ...

Page 6

... HIGH to permit a WRITE to the loaded address. ADV 5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4 LOW. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T35L3232B ADSC extends burst (NOTE5) (NOTE4) ADV suspnds burst ...

Page 7

... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice OELZ D(A3) t OEHZ t KQ Q(A2) Q(A3) Single WRIT E Pass-through READ P. 15 Preliminary T35L3232B A5 D(A5) (NOTE1) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Publication Date: FEB. 2000 A6 D(A6) Back-to-Back WRITEs DON'T CARE UNDEFINED Revision:0.A ...

Page 8

... ( ( Preliminary T35L3232B ( ITE s ...

Page 9

... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T35L3232B DIMENTION IN MM 3.302(MAX) 2.845¡Ó0.127 0.102(MIN) 0.300+0.102-0.051 14.000¡Ó0.127 20.000¡Ó0.127 0.650¡Ó0.152 17.200¡ ...

Page 10

... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T35L3232B DIMENTION IN MM 1.600(MAX) 1.400¡Ó0.050 0.050(MIN) 0.320+0.060-0.100 14.000¡Ó0.100 20.000¡Ó0.100 0.650¡ ...

Page 11

... Address Status Processor: This active LOW input, along with being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address Preliminary T35L3232B DESCRIPTION being LOW. lines and must meet . This input is ADSP Publication Date: FEB ...

Page 12

... DQ32. Input data must meet setup and hold times around the rising edge of CLK. Supply Power Supply: 3.3V +10%/-5% Ground Ground: GND I/O Supply Output Buffer Supply: 3.3V +10%/-5% I/O Ground Output Buffer Ground: GND - No Connect: These signals are not internally conntected Preliminary T35L3232B DESCRIPTION A READ or WRITE cycle is Publication Date: FEB. 2000 Revision:0.A ...

Page 13

... Second Address Third Address (internal) A...A01 A...A10 A...A11 A...A00 BWE BW1 Preliminary T35L3232B Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A10 A...A00 A...A01 A...A01 A...A00 Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 A ...

Page 14

... Current Current BW1 BW2 , BW2 = enables write to DQ9-DQ16. =enables write to DQ25-DQ32. OE and ZZ must meet setup and hold times around the rising edge ( LOW OE P.7 Preliminary T35L3232B ...

Page 15

... Vcc SYM. TYP I CC ADSP ADSC , , BWE , all other I SB1 TBD VCC - 0.2; I SB2 TBD SB3 TBD SB4 TBD P.8 Preliminary T35L3232B greater than those Maximum Ratings" MIN MAX UNITS 2 VCCQ + 0.3 V -0.3 0 2.4 V ...

Page 16

... OEQ 5 t OELZ OEHZ 1.7 2.0 t ADSS 1.7 2.0 t AAS 1.7 2 1.7 2 1.7 2.0 t CES 1.7 2 0.5 0.5 t ADSH 0.5 0.5 t AAH 0.5 0 0.5 0 0.5 0.5 t CEH 0.5 0.5 P.9 Preliminary T35L3232B ( C;VCC=3.3V +0.3V/-0.165V) UNITS -4 2 2.0 ns 2 ...

Page 17

... Deselected means the device is in POWER-DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13.Typical values are measured at 3.3V and 20ns cycle time. 14.MODE pin has an internal pull-up and exhibits an input leakage current of P.10 Preliminary T35L3232B TYP MAX UNITS NOTES SYM ...

Page 18

... ohm 0 Fig. 1 output load equivalent Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T35L3232B 1.5V P.11 3. Fig. 2 output load equivalent Publication Date: FEB. 2000 Revision:0 ...

Page 19

... MODE must not be initiated until valid pending operations are completed. SYMBOL KC) t RZZ P.12 Preliminary T35L3232B is guaranteed after ZZ Therefore, SNOOZE MIN MAX UNITS KC RZZ DON' T CARE Publication Date: FEB. 2000 ...

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