T35L6432A TM Technology Inc., T35L6432A Datasheet - Page 13

• Manufacturer Part Number: T35L6432A
• Description: 64k X 32 Sram 3.3v Supply, Fully Registered Inputs And Outputs, Burst Counter
• Manufacturer: TM Technology Inc.

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READ/WRITE TIMING
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
B W 1- B W 4
A D D R E S S
( N O T E 2 )
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or ADV
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC.
B W E
address following A4.
and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
cycle is performed.
A D S P
A D S C
A D V
C L K
O E
C E
Q
D
CH
TE
A 1
Hig h-Z
t A DSS t A DSH
H i gh -Z
t C E S t C EH
t A S t A H
Back-t o -Back REA Ds
A 2
t KH t KL
t KQL Z
t KC
Q(A1)
t KQ
Q(A 2 )
A 3
t OE HZ
t W S t W H
t DS
Si ng le W RIT E
D(A3)
t DH
A 4
t OELZ
Pas s -th r ough
t KQ
REA D
P. 13
Q(A3 )
(N OT E1)
Q(A4)
Q(A4+1)
BURST REA D
Q(A 4+ 2)
Publication Date: DEC. 1998
Q(A 4+ 3)
T35L6432A
D(A 5 )
A5
Back-to-Back
DO N'T CARE
UNDEFINED
W RIT Es
D(A6)
A 6
Revision:A