T35L6432A TM Technology Inc., T35L6432A Datasheet
T35L6432A
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T35L6432A Summary of contents
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... Each memory cell consists of four transistors and two Q high valued resistors. T The T35L6432A SRAM integrates 65536 x 32 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK) ...
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... DQ17-DQ BW4 controls DQ25-DQ32. BW3 BW4 , , and can be active only with GW being LOW. being LOW causes all WRITE pass-through The T35L6432A operates systems and for systems that are benefited 32 32 OUTPUT OUTPUT 64K SENSE REGISTERS BUFFERS MEMORY AMPS ...
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... READ cycle is initiated using the new address. Input- Address Status Controller:This active LOW input causes device to registered. A READ or WRITE cycle is initiated depending upon write control inputs T35L6432A DESCRIPTION being LOW. lines and must meet . This input is ADSP Publication Date: DEC. 1998 ...
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... DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25- DQ32. Input data must meet setup and hold times around the rising edge of CLK. Supply Power Supply: 3.3V +10%/-5% Ground Ground: GND - No Connect: These signals are not internally conntected T35L6432A DESCRIPTION Publication Date: DEC. 1998 Revision:A ...
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... PRESENT CYCLE OPERATION BWn Register A(n), Q= D(n- D(n- HIGH D(n-1) for one byte P. 5 T35L6432A Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A10 A...A00 A...A01 A...A01 A...A00 Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 A...A01 A ...
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... BW1 BW2 BW3 , , BW2 = enables write to DQ9-DQ16. =enables write to DQ25-DQ32. OE must meet setup and hold times around the rising edge ( LOW to HIGH) OE and staying HIGH throughout the input data hold P. 6 T35L6432A ...
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... Icc 200 300 270 230 190 150 I SB1 56 155 140 125 115 110 ADSP , BWE , all VCC - 0. SB3 SB4 T35L6432A This is a stress rating only and Exposure to absolute maximum rating MIN MAX UNITS 2 VCCQ + 0.3 V -0.3 0.8 ...
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... OEHZ 2 AAS CES 2 0.5 0.5 0.5 t AAH 0.5 0 0.5 0 0.5 0.5 t CEH 0.5 0 T35L6432A TYP MAX UNITS NOTES SYM. QFP TYP UNITS ...
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... C and 20ns cycle time. 14.MODE pin has an internal pull-up and exhibits an input leakage current 1.5V DQ 351 P. 9 T35L6432A ADSP LOW along with chip is a "don't care" when a byte write enable 3.3V 317 5 pF Publication Date: DEC. 1998 ...
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... SYMBOL SB2 KC) t RZZ Vss + 0 T35L6432A is guaranteed after the setup time SB2 Any access pending when entering MIN MAX UNITS KC N'T CARE Vcc -0.2 V). Publication Date: DEC. 1998 ...
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... OEL Q(A 2+1) KQ (NOT E1 T35L6432A A 3 Bur st con tin ase ss. Des ele ct cy cle 2+2) Q( Q(A2 2+1) Bu rst und ita l sta te. BUR ...
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... ( D(A2) D(A2+1) D(A2+1) (NOT RIT T35L6432A exte rst . D(A2 +2) D(A2+3 ) D(A3 ) D(A3+1) E xte RST W RIT E ...
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... OELZ D( RIT E Pas s -th r ough REA T35L6432A A5 D E1) Q(A4) Q(A4+ BURST REA D Back-to-Back Publication Date: DEC. 1998 A 6 D(A6) W RIT Es DO N'T CARE UNDEFINED Revision:A ...
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... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T35L6432A DIMENTION IN MM 3.302(MAX) 2.845¡Ó 0 .127 0.102(MIN) 0.300+0.102-0.051 14.000¡Ó 0 .127 20.000¡Ó 0 .127 0.650¡Ó 0 .152 17.200¡ ...
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... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. Preliminary T35L6432A DIMENTION IN MM 1.600(MAX) 1.400¡Ó 0 .050 0.050(MIN) 0.320+0.060-0.100 14.000¡Ó 0 .100 20.000¡Ó 0 .100 0.650¡ ...