T35L3232B TM Technology Inc., T35L3232B Datasheet - Page 8

• Manufacturer Part Number: T35L3232B
• Description: 32k X 32 Sram Pipeline And Flow-through Burst Mode
• Manufacturer: TM Technology Inc.

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FLOW-THROUGH READ/WRITE TIMING
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
B W 1 - B W 4
AD D R E S S
( N O T E 4 )
( N O T E 2 )
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or ADV
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC .
A D S P
AD S C
B W E
A D V
C L K
O E
C E
address following A4.
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
cycle is performed.
A 1
Q
D
CH
TE
High-Z
t A D S S t A D S H
t C E S t C E H
B a c k -t o -B a c k R E A D s
t A S t A H
Q (A1 )
A 2
t K H t K L
t K C
Q (A2 )
t O E HZ
A 3
t W S t W H
t D S
S i ng le W R IT E
D (A3 )
t D H
A 4
P. 16
t O EL Z
t K Q
Q (A4 )
B U R S T R E A D
Preliminary T35L3232B
(NO TE 1 )
Q (A4 +1 )
Publication Date: FEB. 2000
Q (A4 +2 )
D (A5 )
Q (A4 +3 )
B a c k -to -B a c k
A 5
DO N' T CARE
UNDEFINED
Revision:0.A
W R ITE s
D (A6 )
A 6