T35L3232B TM Technology Inc., T35L3232B Datasheet - Page 6

• Manufacturer Part Number: T35L3232B
• Description: 32k X 32 Sram Pipeline And Flow-through Burst Mode
• Manufacturer: TM Technology Inc.

tm
WRITE TIMING
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
B W 1 - B W 4
A D D R E S S
( N O T E 2 )
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW , CE2 is
3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time.
4.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4
B W E ,
A D S P
ADS C
address following A2.
LOW and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW.
This prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
LOW.
ADV
ADV
C L K
G W
O E
CE
Q
D
CH
TE
must be HIGH to permit a WRITE to the loaded address.
BURST READ
High-Z
t ADSS t ADSH
t CES t CEH
t AS t AH
A1
t KH t KL
(NOTE3)
t OEHZ
BYT E W RIT E s ignals a re
ignored for first cycle when
ADSP init ialtes bu rst.
t KC
t ADSS t ADSH
t DS t DH
Single W RIT E
D(A1)
A2
(NOTE4)
D(A2)
t WS t WH
(NOTE1)
D(A2+1)
BURST W RITE
P. 14
(NOTE5)
D(A2+1)
ADV suspnds burst.
D(A2+2)
ADSC extends burst.
Preliminary T35L3232B
D(A2+3)
t ADSS t ADSH
Publication Date: FEB. 2000
A3
D(A3)
Exte nde d BURST WRITE
t AAS t AAH
t WS t WH
D(A3+1)
DO N' T CARE
UNDEFINED
Revision:0.A
D(A3+2)