T35L3232B TM Technology Inc., T35L3232B Datasheet - Page 4

• Manufacturer Part Number: T35L3232B
• Description: 32k X 32 Sram Pipeline And Flow-through Burst Mode
• Manufacturer: TM Technology Inc.

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PIPELINE READ TIMING
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
G W , B W E ,
B W 1 - B W 4
A D D R E S S
( N O T E 2 )
A D S P
ADS C
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
ADV
C LK
O E
CE
Q
address following A2.
and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
does not cause Q to be driven until after the following clock rising edge.
CH
TE
t ADSS t ADSH
t CES t CEH
t AS t AH
A1
t KH t KL
(NOTE3)
High-Z
t KC
t WS t WH
Sing le READ
t KQLZ
t KQ
t ADSS t ADSH
A2
Q(A1)
t OEHZ
t AAS t AAH
t OELZ
t OEQ
(NOTE1)
Q(A2)
t KQX
t KQ
P. 12
Q(A2+1)
ADV suspends burst.
Q(A2+2)
Preliminary T35L3232B
BURST READ
Q(A2+3)
Publication Date: FEB. 2000
A3
Q(A2)
Burst continued with
new base address.
Burst wraps around
to its inital state.
Q(A2+1)
Deselect cycle.
Revision:0.A
DON' T CARE
UNDEFINED
Q(A3)
t KQHZ
t KQX
OE