DSP56364D Motorola Inc, DSP56364D Datasheet - Page 73
![no-image](/images/no-image-200.jpg)
DSP56364D
Manufacturer Part Number
DSP56364D
Description
24-Bit Audio Digital Signal Processor
Manufacturer
Motorola Inc
Datasheet
1.DSP56364D.pdf
(162 pages)
- Current page: 73 of 162
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MOTOROLA
No.
171 SCL clock frequency
172 Bus free time
173 Start condition set-up time
174 Start condition hold time
175 SCL low period
176 SCL high period
177 SCL and SDA rise time
178 SCL and SDA fall time
179 Data set-up time
180 Data hold time
181 Stop condition set-up time
182 Capacitive load for each line
183 DSP clock frequency
184 HREQ in deassertion to last
Tolerable spike width on SCL
or SDA
Filters bypassed
Narrow filters enabled
Wide filters enabled
SCL edge
(HREQ in set-up time)
Characteristics
Narrow filters enabled
Wide filters enabled
Filters bypassed
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 2-18 SHI I
DSP56364 Advance Information
Go to: www.freescale.com
Expression
Symbol/
T
T
T
T
T
t
T
T
SU;RQI
HD;STA
SU;DAT
HD;DAT
SU;STO
T
SU;STA
F
F
HIGH
LOW
T
C
—
SCL
BUF
DSP
T
Standard I
R
b
F
Serial Host Interface (SHI) I
2
C Protocol Timing
Standard-Mode
10.6
11.8
13.1
Min
250
4.7
4.7
4.0
4.7
4.0
0.0
4.0
0.0
2
—
—
—
—
—
—
—
C*
1000
Max
100
100
300
400
50
—
—
—
—
—
—
—
—
—
—
—
—
0
20 + 0.1
20 + 0.1
28.5
39.7
61.0
Min
100
Fast-Mode
1.3
0.6
0.6
1.3
1.3
0.0
0.6
0.0
—
—
—
—
—
2
C Protocol Timing
C
C
b
b
Specifications
Max
100
400
300
300
400
0.9
50
—
—
—
—
—
—
—
—
—
—
—
0
MHz
MHz
MHz
Unit
2-53
kHz
pF
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
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