DSP56364D Motorola Inc, DSP56364D Datasheet - Page 29

• Manufacturer Part Number: DSP56364D
• Description: 24-Bit Audio Digital Signal Processor
• Manufacturer: Motorola Inc

No.
MOTOROLA
18
19
20
21
24
25
Delay from
tion to general-purpose transfer output valid
caused by first interrupt instruction execution
Delay from address output valid caused by first
interrupt instruction execute to interrupt request
deassertion for level sensitive fast interrupts
Delay from
deassertion for level sensitive fast interrupts
Delay from WR assertion to interrupt request
deassertion for level sensitive fast interrupts
Duration for IRQA assertion to recover from
Stop state
Delay from IRQA assertion to fetch of first
instruction (when exiting Stop)
• DRAM for all WS
• SRAM WS = 1
• SRAM WS = 2, 3
• SRAM WS
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is enabled
(OMR Bit 6 = 0)
• PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is not enabled
(OMR Bit 6 = 1)
• PLL is active during Stop (PCTL Bit 17 =
1) (Implies No Stop Delay)
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
IRQA
RD
Characteristics
assertion to interrupt request
,
IRQB
4
Freescale Semiconductor, Inc.
,
For More Information On This Product,
IRQD
2, 3
DSP56364 Advance Information
,
NMI
Go to: www.freescale.com
asser-
1
1
1
Reset, Stop, Mode Select, and Interrupt Timing
3.75
3.25
PLC
PLC
(WS + 3.5)
(WS + 3.5)
(WS + 2.5)
(WS + 3)
(8.25
T
T
ET
ET
10
C
C
Expression
PLC/2)
C
C
0.5)
+ WS
+ WS
T
PDF + (128 K
PDF + (23.75
0.5)
C
T
T
T
T
+ 5.0
C
T
C
C
C
C
T
T
T
– 10.94
– 10.94
– 10.94
– 10.94
C
C
C
T
– 10.94
– 10.94
C
6
(continued)
105.0
232.5
Min
77.5
5.9
1.3
—
—
—
—
—
—
ns
Specifications
Max
13.6
12.3
87.5
ms
—
—
—
—
—
—
—
—
Unit
2-9
ms
ns
ns
ns
ns
ns