DSP56364D Motorola Inc, DSP56364D Datasheet - Page 11

• Manufacturer Part Number: DSP56364D
• Description: 24-Bit Audio Digital Signal Processor
• Manufacturer: Motorola Inc

1.5.3
RAS0
MOTOROLA
Signal Name
AA0–AA1/
CAS
WR
RD
TA
–
RAS1
External Bus Control
Output
Output
Output
Output
Type
Input
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Freescale Semiconductor, Inc.
Ignored
during
Reset
State
Table 1-7 External Bus Control Signals
Input
For More Information On This Product,
DSP56364 Advance Information
Go to: www.freescale.com
Address Attribute or Row Address Strobe—When defined as AA, these
signals can be used as chip selects or additional address lines. When
defined as
These signals are tri-statable outputs with programmable polarity. These
signals are tri-stated during hardware reset and when the DSP is in the
stop or wait low-power standby mode.
Column Address Strobe—
to strobe the column address. This signal is tri-stated during hardware
reset and when the DSP is in the stop or wait low-power standby mode.
Read Enable—
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
Write Enable—
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
Transfer Acknowledge—If there is no external bus activity, the
is ignored. The
that can extend an external bus cycle indefinitely. Any number of wait
states (1, 2. . .infinity) may be added to the wait states inserted by the
BCR by keeping
the start of a bus cycle, is asserted to enable completion of the bus cycle,
and is deasserted before the next bus cycle. The current bus cycle com-
pletes one clock period after
system clock. The number of wait states is determined by the
by the bus control register (BCR), whichever is longer. The BCR can be
used to set the minimum number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at
least one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result.
synchronously or asynchronously, depending on the setting of the TAS bit
in the operating mode register (OMR).
TA
otherwise improper operation may result.
functionality may not be used while performing DRAM type accesses,
RAS
TA
RD
, these signals can be used as
WR
TA
input is a data transfer acknowledge (DTACK) function
External Memory Expansion Port (Port A)
is an active-low output that is asserted to read exter-
deasserted. In typical operation,
is an active-low output that is asserted to write exter-
Signal Description
CAS
TA
Signal/Connection Descriptions
is asserted synchronous to the internal
is an active-low output used by DRAM
RAS
for DRAM interface.
TA
TA
is deasserted at
can operate
TA
TA
input or
input
1-7