DSP56364D Motorola Inc, DSP56364D Datasheet - Page 28
DSP56364D
Manufacturer Part Number
DSP56364D
Description
24-Bit Audio Digital Signal Processor
Manufacturer
Motorola Inc
Datasheet
1.DSP56364D.pdf
(162 pages)
- Current page: 28 of 162
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No.
Specifications
Reset, Stop, Mode Select, and Interrupt Timing
2.9
2-8
10
13
14
15
16
17
8
9
Delay from
value
Required
Delay from asynchronous
to first external address output (internal reset
deassertion)
Mode select setup time
Mode select hold time
Minimum edge-triggered interrupt request
assertion width
Minimum edge-triggered interrupt request deas-
sertion width
Delay from
tion to external memory access address out
valid
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
• Power on, external clock generator, PLL
disabled
• Power on, external clock generator, PLL
enabled
• Power on, internal oscillator
• During STOP, XTAL disabled
(PCTL Bit 16 = 0)
• During STOP, XTAL enabled
(PCTL Bit 16 = 1)
• During normal operation
• Minimum
• Maximum
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction
execution
3
RESET
RESET
IRQA
5
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
,
duration
IRQB
assertion to all pins at reset
Freescale Semiconductor, Inc.
,
For More Information On This Product,
RESET
IRQD
4
DSP56364 Advance Information
,
NMI
deassertion
Go to: www.freescale.com
asser-
4.25
7.25
20.25 T
3.25
Expression
75000
75000
1000
50
2.5
2.5
—
T
T
T
C
ET
C
C
C
T
T
+ 7.50
ET
ET
ET
+ 2.0
C
C
+ 2.0
+ 2.0
C
C
C
C
500.0
Min
10.0
0.75
0.75
25.0
25.0
34.5
30.0
44.5
74.5
6
0.0
6.6
6.6
—
—
MOTOROLA
211.5
Max
26.0
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
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