MAS281 Dynex, MAS281 Datasheet - Page 42

• Manufacturer Part Number: MAS281
• Description: MIL-STD-1750A Microprocessor
• Manufacturer: Dynex

MAS281
Notes:
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1. Unless otherwise noted, test conditions are as follows: OSC duty cycle = 50%, input rise and fall tlme < 5ns, timing
2. t = 1 OSC period. O 5t implies a 50% OSC duty cycle; fractional t's may be adjusted to reflect actual OSC duty cycle.
7. Measured to pre-Hi-Z steady state 10% of VDD.
9. Output references SYNC, DMAK, and HLDAK drive into load 1.
10. Guaranteed by component LSI testing: not measured on microprocessor module.
SYNC lo to DMAK valid
DMAK valid after SYNC lo
DMAK lo to DD lo
DMAK hi to DD hi
DMAK lo to CD lo
DMAK hi to CD hi
DMAK lo to AD Bus Hi-Z (note 7)
DMAK hi to AD Bus valid (note 10) Load 2
DMAK lo to AS, DS, M/IO, RD/W,
IN/OP Hi-Z (note 7)
DMAK hi to AS, DS, M/IO,
RD/W, IN/OP valid (note 10)
HOLD set up to SYNC lo
HOLD hold after SYNC lo
SYNC lo to HLDAK valid
HLDAK valid after SYNC lo
HLDAK lo to DD lo
HLDAK hi to DD hi
HLDAK lo to CD lo
HLDAK hi to CD hi
HLDAK lo to AD Bus Hi-Z
(Hold) (notes 7 & 10))
HLDAK hi to AD bus
valid (note 10)
HLDAK to AS, DS, M/IO,
RD/W, IN/OP Hi-Z (notes 7 & 10)
HLDAK to AS, DS, M/IO,
RD/W, IN/OP valid (note 10)
Interrupts set up to SYNC lo
Interrupts hold after SYNC lo
Faults setup to SYNC lo
Faults hold after SYNC lo
SYNC lo to SURE, NPU valid
SYNC hi to CONFW valid
TCLK lo to ILLAD lo (Bus timeout)
(note 10)
SYNC lo to ILLAD hi (Bus timeout)
(note 10)
measured from 50% of VDD points.
Parameter
Table 10: Timing Parameters (continued)
Test Condition
(notes 1 & 9)
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 2
Load 2
Load 2
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 2
Load 2
Load 2
Load 1
Load 1
Load 1
Load 1
Load 1
Min.
(note 2)
-
5
-
-
-
-
-
-
-
-
40
15
-
-7
-
-
-
-
-
-
-
-
20
10
20
15
-
-
-
-
Max.
(note 2)
50
-
30
30
30
30
70
60
50
59
-
-
20
-
50
50
50
50
60
50
30
30
-
-
-
-
50
75
75
75
Units
SYNC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns