MAS281 Dynex, MAS281 Datasheet - Page 19

• Manufacturer Part Number: MAS281
• Description: MIL-STD-1750A Microprocessor
• Manufacturer: Dynex

extended 8-bit displacement field within the instruction. This
sum then points to the memory address to which control will be
transferred if the branch is taken.
4.2.7 BASE RELATIVE (B)
Addressing; one allows indexing and one does not. For the
non-indexable form, the contents of the instruction specified
base register (BR = BR’ + 12) is added to the 8-bit
displacement field (DU) of the 16-bit instruction. For the
indexable form, the sum of the contents of a specified index
register and a specified base register is the address of the
required operand. Registers R1 through R15 may be specified
for indexing. Registers R12 through R15 may be specified as
the base register.
4.2.8 SPECIAL
not follow the above formats. The instructions that use this
special mode are indicated in Table 7a.
4.3 BENCHMARKING
associated with each MIL-STD-1750A instruction. This
information may be used when benchmarking MAS281
performance. The Digital Avionics Instruction Set (DAIS) mix,
which defines a typical frequency of occurrence for MIL-STD-
1750A instructions, is used here for this purpose.
reflect the impact of data dependencies on system
performance. For example, a multiplication in which an
operand is zero may be performed much faster than one with
two non-zero operands. Also, the DAIS mix does not specify
such time consuming operations as normalization and
alignment.
instruction mix and data dependencies into account. To this
end, machine cycle counts in Table 7a which have data
dependencies, are annotated with either an "a" or "wa"suffix.
cycles (where each of several possibilities is equally likely) and
a “ "wa" suffix reflects a weighted average number of machine
cycles (where some data possibilities are more likely than
others).
There are two formats which implement Base Relative
This addressing mode is applicable to instructions that do
Table 7a defines the number and type of machine cycles
One problem with the DAIS mix, however, is that it does not
Realistic benchmarks must therefore take both the
An "a" suffix reflects an average number of machine
f
MHz
operations. Weighted averages provided in Table 7a are
based on the Sweeney (IBM) guidelines. These guidelines
take a wide range of data dependencies into consideration.
Normalization and alignment operations are also represented.
Table 6 defines MAS281 throughput, at various frequencies
and wait states, for the DAIS mix using Sweeney data
dependencies.
conservative approach to benchmarking. If best case
assumptions are made and such operations as normalization
and alignment are not considered, MAS281 performance
figures are approximately 50% higher than those indicated in
Table 6.
OSC
Weighted averages are only applicable to floating-point
It should be noted that using the Sweeney guidelines is a
Number of Wait States in Memory Access Cycle
25
20
15
10
743.4
594.7
446.0
297.4
Table 6: Throughput (KIPS)
0
698.3
558.7
419.0
279.3
1
658.4
526.7
395.0
263.4
2
622.8
498.2
373.7
249.1
MAS281
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