MAS281 Dynex, MAS281 Datasheet
MAS281
Related parts for MAS281
MAS281 Summary of contents
Page 1
... Memory Management Unit/Block Protect Unit (MMU(BPU)) chip may be added externally to expand this address space to 1M-words or add a 1K-word memory block protection capability, The MAS281 is offered in several screening grades which are described in this document. For availability of speed grades, please contact Dynex Semiconductor. FEATURES ...
Page 2
... The MAS281 architecture has been optimised for both real time l/O and arithmetic intensive operations. Two key features of this architecture which contribute to the overall high performance of the MAS281 are; a barrel shifter and a parallel multiplier/accumulator. These subsystems allow the MAS281 to perform multi-bit shifts, multiplications, divisions, and normalisations in a fraction of the clock cycles required on machines not having such resources ...
Page 3
... The CS bits are updated after each logical, shift, and arithmetic operation performed by the ALU. The CU interrogates these bits during conditional Figure 2: MAS281 Architecture operations to determine which course of action to follow. The AS field is used during expanded memory access to define the page register set to be used for instruction and operand memory references ...
Page 4
... Carry from an CU over the M bus, buffered by the Execution (E) register, and decoded to generate various control signals. 1.2 CONTROL UNIT (CU) Result >0 The CU provides microprogrammed control of all MAS281 Result = 0 operations. It features a microsequencer, a microcode storage ROM, and an instruction mapping ROM. A brief description of Result<0 these features follows: 1 ...
Page 5
... Table 7b in Section 4.0 identifies the XlO commands which are internally supported by the MAS281. 1.3.8 MICROCODE CONTROL LOGIC Decode logic, which translates microcode received from the CU into control signals, is used both by the MAS281 and by the external system. 2.0 INTERFACE SIGNALS 2.1 PIN ASSIGNMENTS Figure 4 defines the pin assignment for the MAS281 module ...
Page 6
... Full timing characteristics of each of the functions are shown in section 6.0. 2.2.1 POWER AND GROUND (VDD & GND) The MAS281 utilizes a single VDD power supply. A singlepoint ground is provided for the three chips on the substrate and is brought out on two module pins. 2.2.2 OSCILLATOR (OSC) This input clocks the EU state sequencer which, in turn, generates timing and control signals for the rest of the module ...
Page 7
... M/ION is placed in the high impedance state during DMA and Hold cycles and is held high during internal (non-XIO) operations. Figure 5: Typical MAS281/MA31751 System Interface 2.2.8 INSTRUCTION/OPERAND (IN/OP) Output/Hi-Z. This dual function signal indicates the type of data on the AD bus during the data portion of a SYNCN cycle. ...
Page 8
... MAS281 during execution of XIO commands which are implemented in the MA31751 MMU(BPU) chip MA31751 is used with the MAS281, it must reside on the MAS281 local AD bus rather than the system buses (see Figure 5). Table 7b in Section 4.0 identifies those XIO commands which are implemented in the MA31751]. ...
Page 9
... MIL-STD-1750A instruction to be aborted. Although the MAS281 aborts the macroinstruction, system memory management, and / or block protect hardware is responsible for preventing the erroneous bus cycle from accessing memory. To effectively use this feature, MPROEN should be pulled low prior to the high-to-low SYNCN transition of the next machine cycle ...
Page 10
... ROMONLYN is used for testing by GEC Plessey Semiconductors and must be pulled up to VDD in customer applications. 3.0 OPERATING MODES MAS281 operating modes include: (1) initialisation, (2) instruction execution, (3) interrupt servicing, (4) fault servicing, (5) DMA support, (6) Hold support, and (7) timer operations. 3.1 INITIALISATION The module executes a microcoded initialisation routine in response to a hardware reset ...
Page 11
... Label Cycle MAIN Enable Control of DMAE Output signal Clear MAS281 Execution Unit Status Word (SW) Clear Interrupt Mask (MK) (Internal l/O command, SKM 2000H Clear Pending Interrupt Register (Pl) and Fault Register (FT) (Internal l/O Command, CLIR,2001 H) Clear Instruction Counter (IC Disable Interrupts (Internal l/O Command, DSBL,2003H ...
Page 12
... MAS281 3.2 INSTRUCTION EXECUTION Once initialisation has been completed, the module will begin instruction execution. Instruction execution is characterised by a variety of operations, each one or more machine cycles in duration. Depending on the instruction being executed at the time, these operations include: (1) internal CPU cycles, (2) instruction fetches, (3) operand transfers, and (4) input/output transfers ...
Page 13
... MAS281 but is treated, in some ways, like an externally implemented XIO command. This exception is discussed below. Internal l/O transfers involve all XIO commands which are decoded internally either by the MAS281 or by the MA31751 MMU/BPU chip (with the exception noted above). Table 7b identifies these commands ...
Page 14
... MAS281 register on the following SYNC high-to-low transition (with the exception of INT02N which is latched into Pl when INT02N is first detected). This sequence occurs whether interrupts are enabled or disabled or whether the specific interrupt is masked or unmasked. Each external Pl register input is buffered by a falling edge detector to prevent repeat latching of requests held low beyond the first SYNCN high-to-low transition ...
Page 15
... HOLD SUPPORT The Hold state is provided to facilitate debugging of user software by allowing the user to disable the MAS281 and access system resources. Hold state timings is defined in Section 6.0. The Hold state can be entered either by pulling HOLDN low or by executing a BPT instruction with the Console present and indicated in the Configuration Word ...
Page 16
... BPT Hold service routine. This routine decrements IC once, drops HLDAKN low, and enters the Hold state. To release the MAS281 from a BPT initiated Hold state, the HOLDN input must be pulsed low in accordance with the timing diagrams in Section 6.0. When HOLDN returns high, the ...
Page 17
... DTIMERN allows the timers to resume counting from their suspended state and allows timer commands to function normally (DMA control lines are again allowed to change). A feature of the MAS281 timers is the choice of disabling, or not disabling, the interval timers A and B upon execution of a BPT software instruction when a Console is connected. If full ...
Page 18
... MAS281 Figure 9: Register Set Model 4.2.4 IMMEDIATE LONG (IM, IMX) There are two formats which implement Immediate Long Addressing; one allows indexing and one does not. For the indexable form, if the specified index register, RX, is not equal to zero, the contents of RX are added to the immediate field to form the required operand ...
Page 19
... Sweeney (IBM) guidelines. These guidelines take a wide range of data dependencies into consideration. Normalization and alignment operations are also represented. Table 6 defines MAS281 throughput, at various frequencies and wait states, for the DAIS mix using Sweeney data dependencies. It should be noted that using the Sweeney guidelines is a conservative approach to benchmarking ...
Page 20
... MAS281 20/55 Figure 11: Addressing Modes ...
Page 21
... STCI 0X DSTB 4X 3 DSTX 96 DST 98 DSTI STM ABX A2 AISP AIM A3 INCM A4 ABS A5 DABS Table 7a: Instruction Summary MAS281 Cycles * Format ISP 1 0 ISN IM,IMX ...
Page 22
... MAS281 Operation Double-Precision Integer Add Single Precision Integer Subtract Decrement Memory by a Positive Integer Single Precision Negate Register Double-Precision Negate Register Double-Precision Integer Subtract Single Precision Integer Multiply with 16-Bit Product Single Precision Integer Multiply with 32-Bit Product Double-Precision Integer Multiply ...
Page 23
... TBR TBI 59 TSB 5A SVBR 5C RVBR 5E TVBR 97 SRM 8B LUB 8D LUBI 8C LLB 8E LLBI 9B STUB 9D SUB I 9C STLB 9E SLBI EC XBR Table 7a: Instruction Summary (continued) MAS281 Format Cycles * ...
Page 24
... MAS281 Operation COMPARE Single-Precision Compare Compare Between Limits Double-Precision Compare JUMP/BRANCH Jump on Condition Jump to Subroutine Subtract One and Jump Branch Unconditionally Branch if Equal to (Zero) Branch if Less than (Zero) Branch to Executive Branch if Less than or Equal to (Zero) Branch if Greater than (Zero) Branch if Not Equal to (Zero) ...
Page 25
... Table 7a: Instruction Summary (continued) Format Cycles * 4. 12. 7 2.5+n 2.25+n (n=O to 15) (n (n=O to 15) (n=O to 15) IM,IMX 3 3.583 D, 1+4n 1+ MAS281 B 4.5a 2a 6.25a 3. 4.25a 2a 6.277a - 1+2na 25/55 ...
Page 26
... MAS281 Operation FLOATING-POINT Extended-Precision Floating- Point Load Extended-Precision Floating- Point Store Floating-Point Absolute Value of Register Floating-Point Negate Register Floating-Point Compare Extended-Precision Floating- Point Compare Floating-Point Add Extended-Precision Floating- Point Add Floating-Point Subtract Extended-Precision Floating- Point Subtract Floating-Point Multiply Extended-Precision Floating- point Multiply ...
Page 27
... INTERNAL I/O COMMAND SUMMARY Operation Implemented in MAS281 Set Fault Register Set Interrupt Mask Clear Interrupt request Enable Interrupts Disable Interrupts Reset Pending Interrupt Set Pending Interrupt Register Reset Normal Power Up Discrete Write Status Word Enable Start-Up ROM Disable Start-Up ROM Direct Memory Access Enable ...
Page 28
... MAS281 5.0 TIMING CHARACTERISTICS & DIAGRAMS This section provides detailed timing specifications for the MAS281, under the test loads detailed below. Cross hatching in all figures indicates either a “don't care” or undeterminate state. Load 2 Load 3 28/55 *Includes all jig and parasitic capacitance ...
Page 29
... Figure 12: Reset Timing Figure 13: Internal CPU Operations MAS281 29/55 ...
Page 30
... MAS281 NOTES: 1. Dashed timing lines indicate no-wait cycle timing. 2. Other output states HIGH and DMAK = HIGH 3. Other required input states: HOLD = HIGH, DMAR = HIGH and RESET = LOW. 30/55 Figure 14: Write Transfer Timing ...
Page 31
... NOTES: 1. Dashed timing lines indicate no-wait cycle timing. 2. Other output states HIGH, HLDAK = HIGH and DMAK = HIGH 3. Other required input states: HOLD = HIGH, DMAR = HIGH and RESET = LOW. Figure 15: Read Transfer Timing. MAS281 31/55 ...
Page 32
... MAS281 NOTES: 1. Dashed timing lines indicate no-wait cycle timing. 2. Other output states HIGH, HLDAK = HIGH and DMAK HIGH 3. Other required input states: HOLD = HIGH, DMAR = HIGH and RESET = LOW. 32/55 Figure 16: Internal I/O Write/Command ...
Page 33
... NOTES: 1. Dashed timing lines indicate no-wait cycle timing. 2. Other output states HIGH, HLDAK = HIGH and DMAK HIGH 3. Other required input states: HOLD = HIGH, DMAR = HIGH and RESET = LOW. Figure 17: Internal I/O Read Timing MAS281 33/55 ...
Page 34
... MAS281 NOTE: Other required input states: DTIMER = HIGH and RESET = LOW NOTE: Other required input: RESET = LOW 34/55 Figure 18: DMA Access/Release Timing Figure 19: Interrupt Request Timing ...
Page 35
... TCLK falling edges during a continuous DS = low are necessary to cause a bus fault timeout. 2. Other output states: HLDAK = HIGH. 3. Other required input states: DTO = HIGH and RESET = LOW. NOTES: 1. Assumes only one fault active at a time. 2. Buffered EXADE. 3. Other required input state: RESET = LOW. Figure 20: Bus Fault Timeout Timing Figure 21: Fault Capture Timing MAS281 35/55 ...
Page 36
... MAS281 NOTES: 1. The "don't care" state will continue to exist until HLDAK = HIGH, RDY will then resume normal operation. 2. HOLD falling may occur at any time during software execution. The diagram shows the last possible time it can occur and be assured of entering the HOLD state after the current instruction completes execution. ...
Page 37
... NOTES: 1. ADDRESS = IC(BPT) initiated the Hold state. ADDRESS = IC(Hold HOLD = LOW initiated the Hold state (unless changed by the monitor system). 2. Other output states: DMAK HIGH. 3. Other required input states: DMAR = HIGH and RESET = LOW. Figure 23: Hold State Termination Timing MAS281 37/55 ...
Page 38
... MAS281 NOTES: 1. Other required input: RESET = LOW. 2. TCLK/10 is the internally derived Timer B clock. 3. Timers A and B are clocked on the second SYNC falling edge after TCLK set-up time is satisfied. 38/55 Figure 24: Timer Operations ...
Page 39
... NOTES: 1. Other required input states: RESET = LOW. Figure 25: Discrete Outputs Timing MAS281 39/55 ...
Page 40
... MAS281 6.0 ABSOLUTE MAXIMUM RATINGS Parameter Min Supply voltage -0.5 Input voltage -0.3 Current through any pin -20 Operating temperature -55 Storage temperature -65 Table 8: Absolute Maximum Ratings DEFINITION OF SUBGROUPS Subgroup Definition 1 Static characteristics specified in Table Static characteristics specified in Table 9 at +125 C 3 Static characteristics specified in Table 9 at -55 C ...
Page 41
... 4 MAS281 41/55 ...
Page 42
... MAS281 NO. Parameter 31 SYNC lo to DMAK valid 32 DMAK valid after SYNC lo 33 DMAK DMAK DMAK DMAK DMAK Bus Hi-Z (note 7) 38 DMAK Bus valid (note 10) Load 2 39 DMAK lo to AS, DS, M/IO, RD/W, IN/OP Hi-Z (note 7) 40 DMAK hi to AS, DS, M/IO, ...
Page 43
... Output references SYNC, DMAK, and HLDAK drive into load 1. 10. Guaranteed by component LSI testing: not measured on microprocessor module. Test Condition (notes 1 & 9) Load 1 Load 1 Load 1 Load 1 Load 1 Load 1 Load 1 Load 1 Load 1 (DS), Load 2 (Data) Table 10: Timing Parameters (continued) MAS281 Min. Max. Units (note 2) (note 150 ...
Page 44
... MAS281 9.0 CHIP SET INTERCONNECTION To form the MAS281 processor from the individual chips MA17501, MA17502 and MA17503, connects should be made as shown below. 44/55 Figure 26: Chip Set Interconnection Diagram ...
Page 45
... PACKAGING INFORMATION DUAL-IN-LINE CERAMIC MODULE (MAS281 - PACKAGE TYPE C) Pin 1 3.200 0.032 3.100 Figure 27: Dimensioned Drawing MAS281 1.100 0.900 0.011 0.020 0.100 0.220 max 0.110 0.010 0.100 typ 0.280 0.015 45/55 ...
Page 46
... MAS281 FLATPACK CERAMIC MODULE (MAS281 - PACKAGE TYPE F) Pin 1 46/55 3.200 0.032 Figure 28a: Dimensioned Drawing 1.100 2.100 max 0.011 0.100 0.220 max Dimensions in Inches ...
Page 47
... AD11 Figure 28b: Pin Assignment for Dual-In-Line (Type C) and Flatpack (Type F) Ceramic Modules MAS281 47/55 ...
Page 48
... MAS281 CERAMIC DUAL-IN-LINE (MA17501 TO MA17503 - PACKAGE TYPE C) 48/ GPS XG413 Figure 29a: Dimensioned Drawing Ref. Min. Nom 0.040 - b 0.014 - c 0.009 - 0.100 typ e1 - 0.900 typ H 0.185 - Dimensions in Inches Max. 0.225 0.060 0.020 0.014 3.230 - - 0.212 0.920 0.050 ...
Page 49
... HLDAKN NC S9 PAUSEN GND OVIN NC 62 IRDYN T1 63 RDYN RESET 64 SYNCN HOLDN Figures 29b: Pin Assignments MAS281 17503 ILLADN DTON SYNCLKN DSN INTREN CONFWN IRDYN M/ION DMAKN DMAE DMARN M04 M05 M06 TCLK AD00 AD01 AD02 AD03 AD04 AD05 ...
Page 50
... MAS281 LEADLESS CHIP CARRIER (MA17501 PACKAGE TYPE L) 0.087 max 0.670 0.007 50/55 0.720 + 0.013, 0.008 SQ. 0.020 0.060 Pin No.1 Index GPS XG493 Figure 30a: Dimensioned Drawing 0.040 ...
Page 51
... HLDAKN NC 59 PAUSEN GND OVIN NC 62 IRDYN T1 63 RDYN RESET 64 SYNCN HOLDN Figures 30b: Pin Assignments MAS281 17503 ILLADN DTON SYNCLKN DSN INTREN CONFWN IRDYN M/ION DMAKN DMAE DMARN M04 M05 M06 TCLK AD00 AD01 AD02 AD03 AD04 AD05 ...
Page 52
... MAS281 TOPBRAZE FLATPACK (MA17501 PACKAGE TYPE F) 0.400 0.415 0.107 max 52/55 0.940 0.960 0.065 0.050 0.085 nom. Figure 31a: Dimensioned Drawing 0.008 0.012 0.016 0.020 Pin No.1 GPS XG540 ...
Page 53
... NC 62 HLDAKN GND 63 PAUSEN OVIN NC 66 IRDYN T1 67 RDYN RESET 68 SYNCN HOLDN Figure 31b: Pin Assignments MAS281 17503 NC ILLADN DTON SYNCLKN DSN INTREN CONFWN IRDYN M/ION DMAKN DMAE DMARN M04 M05 M06 TCLK AD00 AD01 AD02 AD03 AD04 AD05 ...
Page 54
... MAS281 11.0 RADIATION TOLERANCE Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose ...
Page 55
... UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. © Dynex Semiconductor 2000 Publication No. DS3563-5 Issue No. 5.0 January 2000 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM MAS281 Manufacturing Code of component ic's Speed Grading ...