MAS281 Dynex, MAS281 Datasheet - Page 13

• Manufacturer Part Number: MAS281
• Description: MIL-STD-1750A Microprocessor
• Manufacturer: Dynex

which is decoded by the MAS281 but is treated, in some ways,
like an externally implemented XIO command. This exception
is discussed below.
decoded internally either by the MAS281 or by the MA31751
MMU/BPU chip (with the exception noted above). Table 7b
identifies these commands. The A, Dl and DO registers are
used as in operand transfers. Internal l/O transfers are
characterised by DDN staying high for the duration of the
transfer in order to prevent bus contention between the module
AD bus and the system bus. Machine cycle associated with
internal I/O commands are normally six oscillator cycles in
duration but might be extended to seven OSC cycles by the
internal ready interface if the module is run at high frequencies.
Internal I/O transfers may be subdivided into writes, reads and
commands as follows:
value to be written. The command is placed on the AD bus
from the A register at the SYNCN high-to-low transition and is
assured valid on the high-to-low transition of AS. The value to
be written is placed on the AD bus from the DO register at the
SYNCN low-to-high transition and is written to the internal l/O
device by the subsequent SYNCN high-to-low transition. An
example of an internal l/O write is loading timer A.
value returned by the internal device. The command is placed
on the AD bus from the A register at the SYNCN high-to-low
transition and is assured valid on the highto-low transition of
AS. The internal l/O device places the value to be read on the
I/O reads consist of a command phase followed by the
Note: BIT pass is indicated by all zeros in FT bits 13,14, and 15.
Internal l/O transfers involve all XIO commands which are
I/O writes consist of a command phase followed by the
BIT
1
2
3
4
5
-
Microcode Sequencer
IB Register Control
Barrel Shifter
Byte Operations and Flags
Temporary Registers (T0 - T7)
Microcode Flags
Multiply
Divide
Interrupt Unit- MK, Pl, FT
Enable/Disable Interrupts
Status Word Control
User Flags
General Registers (R0 - R15)
Timer A
Timer B
BIT Pass/Fail Overhead
Test Coverage
Table 4: Built-in Test Coverage and Tuning
BIT Fail Codes (FT 13,14,15)
100
101
111
110
111
-
AD bus at the SYNCN low-tohigh transition. This value is
captured by the Dl register on the subsequent SYNCN high-to-
low transition. An example of such an operation is reading the
interrupt mask register.
command is placed on the AD bus from the A register at the
SYNCN high-to-low transition and is executed at the following
SYNCN high-to-low transition. An example of an l/O command
is raising the DMAE discrete.
with the following exceptions: (1) DDN goes low, as with
operand transfers, during an l/O read; and (2) external l/O
machine cycles are normally five OSC cycles in duration and
may be extended via the RDYN signal as with operand
transfers.
command is a special case. It is decoded internally to generate
a read strobe (CONFWN) and therefore uses both the
standard internal I/O six OSC period machine cycle as well as
the internal ready interface to extend its cycle. It relies on an
externally implemented configuration register, however, and
therefore cycles DDN as with external I/O cycles. Therefore,
the configuration word register must reside on the system side
of the data bus transceivers as opposed to residing directly on
the local AD bus (as shown in Figure 5).
programmed response to asynchronous system events. A low
on any of these inputs will be detected at the high-to-low
transition of SYNCN and latched into the Pending Interrupt (Pl)
I/O commands consist of a command phase alone. The
External l/O transfers are similar to internal l/O transfers
As discussed earlier, the Read Configuration Word
Nine user interrupt request inputs are provided for
Cycles
220
165
216
155
775
25
MAS281
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