HT48E10 Holtek Semiconductor, HT48E10 Datasheet - Page 7

• Manufacturer Part Number: HT48E10
• Description: I/O Type 8-Bit MTP MCU
• Manufacturer: Holtek Semiconductor

Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent four return ad-
dresses are stored).
Data Memory - RAM
The data memory has a capacity of 81 8 bits and is di-
vided into two functional groups: special function regis-
ters and general purpose data memory (64 8). Most
are read/write, but some are read only.
The unused space before 40H is reserved for future ex-
panded usage and reading these locations will return
the result 00H . The general purpose data memory,
addressed from 40H to 7FH, is used for data and control
information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
memory pointer registers (MP). The control register of
the EEPROM data memory is located at [40H] in Bank 1.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration on [00H] and [02H] access the RAM pointed to
by MP0 (01H) and MP1 (03H), respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
Rev. 1.50
CLR [m].i . They are also indirectly accessible through
7
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory in Bank 0, while MP1 can be applied to data
memory in Bank 0 and Bank 1.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. Data move-
ment between two data memory locations must pass
through the accumulator.
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
The ALU not only saves the results of a data operation
but also changes the status register.
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
RAM Mapping
October 31, 2006
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HT48E10